Asynchronous sample rate converter
View Patent ↗Various embodiments perform sample rate conversion of a sample series at an input rate to an output rate. A version of the sample series is corrected with timing error information generated by a digital loop. The digital loop is locked to a first rate and clocked at a second rate.
1. A method, comprising:
performing sample rate conversion of a sample series at an input rate to an output rate, the output rate being different from any integer multiple of the input rate, including:
correcting a version of the sample series with timing error information generated by a digital loop, the digital loop locked to a first rate being a multiple of the input rate and clocked at a second rate being a multiple of the output rate, the second rate being different from any integer multiple of the first rate.
2. The method of claim 1 , wherein the first rate is the multiple of the input rate, the multiple of the input rate being one, such that the version of the sample series is equal to the sample series at the input rate.
3. The method of claim 1 , wherein the first rate is the multiple of the input rate, the multiple of the input rate being an integer greater than one, such that the version of the sample series is an oversampled version of the sample series at the input rate.
4. The method of claim 1 , wherein the second rate is the multiple of the output rate, the multiple of the output rate being one, such that the second rate is equal to the output rate.
5. The method of claim 1 , wherein the second rate is the multiple of the output rate, the multiple of the output rate being an integer greater than one.
6. The method of claim 1 , further comprising:
generating the version of the sample series by clocking at the second rate, the version of the sample series including timing errors due to clocking at the second rate rather than any integer multiple of the input rate.
7. The method of claim 1 , wherein said performing further comprises:
correcting amplitudes of the version of the sample series with the timing error information.
8. The method of claim 1 , further comprising:
generating, with arithmetic circuitry, a plurality of modular overflows at an overflow rate adjusted to the first rate locking the digital loop, each of the plurality of modular overflows indicating generation by the arithmetic circuitry of timing error information between the first rate and the second rate.
9. The method of claim 1 , wherein the sample series at the input rate is from an S/PDIF (Sony/Philips Digital Interface Format) signal.
10. The method of claim 1 , wherein the sample rate conversion has a dynamic range limited primarily by input quantization noise.
11. The method of claim 1 , wherein the sample rate conversion has a dynamic range limited primarily by input quantization noise, image rejection of an oversampling finite impulse response filter, and image rejection of a downsampling finite impulse response filter.
12. The method of claim 1 , wherein the sample rate conversion has a maximum downsampling ratio limited primarily by the output rate.
13. The method of claim 1 , wherein the sample rate conversion has a maximum oversampling ratio limited primarily by a rate limitation characterizing logic synthesis of the circuit.
14. A circuit performing sample rate conversion of a sample series at an input rate to an output rate, the output rate being different from any integer multiple of the input rate, comprising:
a digital loop locked to a first rate being a multiple of the input rate and clocked at a second rate being a multiple of the output rate, the second rate being different from any integer multiple of the first rate, including:
frequency detection and low pass filter circuitry; and
variable oscillator circuitry forming the digital loop with the frequency detection and low pass filter circuitry,
wherein the digital loop generates timing error information; and
circuitry correcting the version of the sample series with the timing error information.
15. The circuit of claim 14 , wherein the first rate is the multiple of the input rate, the multiple of the input rate being one, such that the version of the sample series is equal to the sample series at the input rate.
16. The circuit of claim 14 , wherein the first rate is the multiple of the input rate, the multiple of the input rate being an integer greater than one, such that the version of the sample series is an oversampled version of the sample series at the input rate.
17. The circuit of claim 14 , wherein the second rate is the multiple of the output rate, the multiple of the output rate being one, such that the second rate is equal to the output rate.
18. The circuit of claim 14 , wherein the second rate is the multiple of the output rate, the multiple of the output rate being an integer greater than one.
19. The circuit of claim 14 , further comprising:
circuitry generating the oversampled version of the sample series by clocking at the second rate, the oversampled version including timing errors due to clocking at the second rate rather than any integer multiple of the input rate.
20. The circuit of claim 14 , further comprising:
circuitry correcting amplitudes of the oversampled version of the sample series with the timing error information.
21. The circuit of claim 14 , wherein the variable oscillator circuitry includes finite modulus arithmetic circuitry.
22. The circuit of claim 14 , wherein the digital loop generates timing error information between the input rate and the second rate.
23. The circuit of claim 14 , wherein the digital loop generates timing error information between the first rate and the second rate.
24. The circuit of claim 14 , wherein the variable oscillator circuitry includes carry adder circuitry, the carry adder circuitry including:
more significant bit circuitry; and
less significant bit circuitry coupled to the more significant bit circuitry, wherein the less significant bit circuitry generates an overflow, the overflow indicating generation by the carry adder circuitry of timing error information between the input rate and the second rate.
25. The circuit of claim 14 , wherein the variable oscillator circuitry includes carry adder circuitry, the carry adder circuitry including:
more significant bit circuitry; and
less significant bit circuitry coupled to the more significant bit circuitry, wherein the less significant bit circuitry generates an overflow, the overflow indicating generation by the carry adder circuitry of timing error information between the first rate and the second rate.
26. The circuit of claim 14 , wherein the sample series at the input rate is from an S/PDIF (Sony/Philips Digital Interface Format) signal.
27. The circuit of claim 14 , further comprising an input integrated with the circuit, the input receiving the sample series at the input rate from an S/PDIF (Sony/Philips Digital Interface Format) signal.
28. The circuit of claim 14 , wherein the circuit has a dynamic range limited primarily by input quantization noise.
29. The circuit of claim 14 , wherein the circuit has a dynamic range limited primarily by input quantization noise, image rejection of an oversampling finite impulse response filter, and image rejection of a downsampling finite impulse response filter.
30. The circuit of claim 14 , wherein the circuit has a maximum downsampling ratio limited primarily by the output rate.
31. The circuit of claim 14 , wherein the circuit has a maximum oversampling ratio limited primarily by a rate limitation characterizing logic synthesis of the circuit.
32. A circuit, comprising:
means for performing sample rate conversion of a sample series at an input rate to an output rate, the output rate being different from any integer multiple of the input rate, including:
means for correcting a version of the sample series with timing error information generated by a digital loop, the digital loop locked to a first rate being a multiple of the input rate and clocked at a second rate being a multiple of the output rate, the second rate being different from any integer multiple of the first rate.