Method and system for configuring a tower top low noise amplifier
View Patent ↗Controlling a tower-top low noise amplifier (TTLNA) without transmit mode or receive mode timing control signals from a base station. The TTLNA system and associated components autonomously determine the proper mode of operation (transmit/receive), and automatically control the operation of a low noise amplifier (LNA) to prevent signal distortion and/or damage to the wireless system hardware. A preferred method comprises: at a TTLNA, measuring a transmit time period based on detecting radio frequency (RF) transmit signal energy; determining a receive time duration based on the measured time period and a predetermined frame time; and, configuring the TTLNA to a receive mode by placing a low noise amplifier into a receive signal path during the determined receive time duration.
1. A method of controlling a tower-top low noise amplifier (TTLNA) comprising:
configuring a TTLNA to the transmit mode by removing a low noise amplifier (LNA) from a receive signal path, wherein removing the LNA from a receive path includes grounding an input of the LNA and terminating the output of the LNA;
at a TTLNA receive duration timing circuit, detecting a start of a radio frequency (RF) transmit signal and an end of an RF transmit signal and responsively generating a receive mode control signal;
configuring a TTLNA to the receive mode by placing the LNA into the receive signal path in response to detecting the end of the RF transmit signal; and
returning the TTLNA to the transmit mode in response to the receive mode control signal generated at the TTLNA in response to the receive duration timing circuit.
2. The method of claim 1 wherein the step of detecting a start of an RF transmit signal and an end of an RF transmit signal is performed by a power detection circuit.
3. The method of claim 1 wherein the receive duration timing circuit comprises a counter circuit.
4. The method of claim 3 wherein an output from the counter circuit is used to generate the receive mode control signal to terminate a receive period.
5. The method of claim 3 wherein an output from the counter is used to interrupt a processor which generates the receive mode control signal to terminate a receive period.
6. The method of claim 1 wherein the receive duration timing circuit includes a microprocessor for generating the receive mode control signal.
7. The method of claim 1 wherein the receive duration timing circuit includes a counter circuit and a latch circuit for generating the receive mode control signal.
8. The method of claim 1 wherein the receive mode control signal provides a time delay before placing the LNA in the receive signal path after the detection of the end of the RF transmit signal.
9. The method of claim 1 further comprising providing the receive mode control signal to a second LNA in a second receive signal path.
10. The method of claim 1 further comprising generating an alarm signal when the start of an RF transmit signal is not detected during a predetermined time.
11. The method of claim 1 further comprising receiving a command signal that overrides the receive mode control signal and responsively placing the TTLNA into either the transmit mode or the receive mode.
12. A tower-top low noise amplifier assembly (TTLNA) comprising:
a low noise amplifier (LNA) switchably coupled to a receive signal path;
a power detection circuit coupled to a transmit signal path for generating a transmit power signal indicative of transmit energy being present;
a receive timing circuit coupled to the power detection circuit for generating a receive mode control signal in response to the transmit power signal, wherein the receive timing circuit comprises a counter that is started in response to the transmit power signal, and provides an output indicative of the end of a frame time; and
wherein the receive timing circuit is coupled to the LNA and the receive mode control signal is used to couple and decouple the LNA from the receive signal path.
13. The TTLNA assembly of claim 12 wherein the receive timing circuit comprises a microprocessor.
14. The TTLNA assembly of claim 13 wherein the receive timing circuit further comprises a counter for generating a microprocessor interrupt signal indicating an end of frame time.
15. The TTLNA assembly of claim 1 wherein the counter is configurable for a desired time duration.
16. The TTLNA assembly of claim 12 wherein the receive mode control signal indicates an end of a receive time period that precedes the beginning of a transmit time period by a predetermined guard interval.
17. The TTLNA assembly of claim 16 wherein the guard time interval is controlled by configuring a counter.