Superconducting shielding for use with an integrated circuit for quantum computing
View Patent ↗An integrated circuit for quantum computing may include a superconducting shield to limit magnetic field interactions.
1. An integrated circuit for quantum computing comprising:
a first metal layer including
at least a portion of a first superconducting qubit and
at least a portion of a second superconducting qubit;
a second metal layer including
a superconducting plane,
wherein at least a portion of the superconducting plane underlies the at least a portion of the first superconducting qubit and the at least a portion of the second superconducting qubit to form
a shielded region of the integrated circuit,
the at least a portion of the first superconducting qubit and the at least a portion of the second superconducting qubit are magnetically isolated from one another within the shielded region; and
a first dielectric layer between at least a portion of the first metal layer and at least a portion of the second metal layer.
2. The integrated circuit of claim 1 wherein the first superconducting qubit and the second superconducting qubit do not use the superconducting plane as a ground plane.
3. The integrated circuit of claim 1 further comprising at least one additional dielectric layer and at least one additional metal layer.
4. The integrated circuit of claim 1 wherein the first metal layer and the second metal layer are each composed of a superconducting material.
5. The integrated circuit of claim 4 wherein the superconducting material is selected from the group consisting of aluminium and niobium.
6. The integrated circuit of claim 1 wherein a distance separating the at least a portion of the first superconducting qubit and the at least a portion of the second superconducting qubit is less than two times a distance separating the first metal layer and the second metal layer.
7. The integrated circuit of claim 1 , further comprising;
a second portion of the first superconducting qubit and
a second portion of the second superconducting qubit,
wherein the superconducting plane does not underlie the second portion of the first superconducting qubit and the second portion of the second superconducting qubit, to thereby form an unshielded region of the integrated circuit, and wherein
the second portion of the first superconducting qubit and the second portion of the second superconducting qubit are not magnetically isolated from one another within the unshielded region.
8. The integrated circuit of claim 1 ,
wherein the first metal layer includes
at least a portion of a third superconducting qubit and
at least a second portion of the first superconducting qubit, and
wherein the superconducting plane does not underlie the at least a portion of the third superconducting qubit and the second portion of the first superconducting qubit,
to thereby form an unshielded region of the integrated circuit, and
wherein the third superconducting qubit and the first superconducting qubit are magnetically coupled to one another within the unshielded region.
9. The integrated circuit of claim 1 wherein at least one of the first superconducting qubit and the second superconducting qubit is a superconducting flux qubit.
10. The integrated circuit of claim 1 wherein the superconducting plane is sized and positioned so that the shielded region covers a majority of the integrated circuit.
11. The integrated circuit of claim 1 wherein the first dielectric layer has a thickness within the range of 50 nm to 1000 nm.
12. The integrated circuit of claim 1 wherein at least one of the first metal layer and the second metal layer has a thickness within the range of 50 nm to 500 nm.
13. An integrated circuit for quantum computing comprising:
a first superconducting qubit;
a second superconducting qubit;
a superconducting metal layer; and
a dielectric layer that separates the superconducting metal layer from both the first superconducting qubit and the second superconducting qubit,
wherein at least a portion of the superconducting metal layer underlies
at least a portion of the first superconducting qubit and
at least a portion of the second superconducting qubit,
wherein the at least a portion of the superconducting metal layer shields a shielded region of the integrated circuit, and
wherein a magnetic field produced by the first superconducting qubit within the shielded region is attenuated in proportion to 1/r 3 ,
where r is a distance from the first superconducting qubit.
14. The integrated circuit of claim 13 , further comprising:
an unshielded region of the integrated circuit in which the superconducting metal layer does not underlie
a second portion of the first superconducting qubit and
a second portion of the second superconducting qubit,
and wherein a magnetic field produced by the first superconducting qubit within the unshielded region is attenuated in proportion to 1/r.
15. The integrated circuit of claim 14 wherein the first superconducting qubit and the second superconducting qubit are magnetically coupled within the unshielded region.
16. The integrated circuit of claim 13 wherein the first superconducting qubit and the second superconducting qubit do not use the superconducting metal layer as a ground plane.
17. The integrated circuit of claim 13
wherein the first superconducting qubit, the second superconducting qubit, and the superconducting metal layer are each comprised of
a superconducting material that is selected from the group consisting of aluminium and niobium.
18. The integrated circuit of claim 13 wherein the first superconducting qubit and the second superconducting qubit are magnetically isolated from each other in the shielded region.
19. The integrated circuit of claim 13 wherein at least one of the first superconducting qubit and the second superconducting qubit is a superconducting flux qubit.
20. The integrated circuit of claim 13
wherein the superconducting metal layer is sized and positioned so that the shielded region covers a majority of the integrated circuit.
21. The integrated circuit of claim 13 wherein the superconducting metal layer has a thickness within the range of 50 nm to 500 nm.
22. The integrated circuit of claim 13 , further comprising:
a third superconducting qubit,
wherein the dielectric layer separates the superconducting metal layer from the third superconducting qubit, and
the superconducting metal layer does not underlie
at least a portion of the third superconducting qubit and
a second portion of the first superconducting qubit, to thereby define an unshielded region of the integrated circuit characterized in that a magnetic field produced by the first superconducting qubit within the unshielded region is attenuated in proportion to 1/r.
23. The integrated circuit of claim 22 wherein the third superconducting qubit and the first superconducting qubit are magnetically coupled to one another in the unshielded region.