Thin film transistor for flat panel display and method of fabricating the same

1. A thin film transistor of a flat panel display including:

a substrate on which an insulating layer is deposited,

a semiconductor layer, which is a layer having width and length on the insulating layer, provided with doping regions in a letter U shape and a channel region situated between the doping regions;

a gate insulating layer formed on the semiconductor layer;

a gate electrode formed on the gate insulating layer to traverse the doping region; and

a protrusion, which is a part of the gate electrode, formed on the gate insulating layer to be opposed to the channel region.

2. The thin film transistor of the flat panel display as claimed in claim 1 , wherein the insulating layer is SiN x or SiO 2 .

3. The thin film transistor of the flat panel display as claimed in claim 1 , wherein the semiconductor layer is amorphous silicon or polycrystalline silicon.

4. The thin film transistor of the flat panel display as claimed in claim 1 , wherein the insulating layer is SiN x or SiO 2 .

5. The thin film transistor of the flat panel display as claimed in claim 1 , wherein the gate electrode is Mo or MoW.

6. A method of fabricating a thin film transistor of a flat panel display comprising:

depositing an insulating layer on a substrate,

forming a semiconductor layer, which is a layer having width and length on the insulating layer, wherein the semiconductor layer is provided with doping regions in a letter U shape and a channel region situated between the doping regions;

forming a gate insulating layer on the semiconductor layer;

forming a gate electrode on the gate insulating layer to traverse the doping region; and

forming a protrusion, which is a part of the gate electrode, on the gate insulating layer to be opposed to the channel region.

7. The method of fabricating the thin film transistor of the flat panel display as claimed in claim 6 , wherein the insulating layer is SiN x or SiO 2 .

8. The method of fabricating the thin film transistor of the flat panel display as claimed in claim 6 , wherein the semiconductor layer is amorphous silicon or polycrystalline silicon.

9. The method of fabricating the thin film transistor of the flat panel display as claimed in claim 6 , wherein the insulating layer is SiN x or SiO 2 .

10. The method of fabricating the thin film transistor of the flat panel display as claimed in claim 6 , wherein the gate electrode is Mo or MoW.

11. A thin film transistor of a flat panel display, comprising:

a semiconductor layer having doped regions and a channel region positioned between the doped regions;

a gate insulating layer formed on the semiconductor layer; and

a gate structure formed on the gate insulating layer and including a primary gate and a secondary gate, the primary gate being formed over the doped regions and across the channel region to switch the thin film transistor, and the secondary gate being formed over the channel region to switch the thin film transistor if a short circuit is formed between the doped regions.

12. The thin film transistor of a flat panel display as claimed in claim 11 , wherein the gate structure includes a gate electrode, a first portion of the gate electrode that extends over the doped regions and across the channel region being the primary gate, and a second portion of the gate electrode that extends from the first portion being the secondary gate.

13. The thin film transistor of a flat panel display as claimed in claim 11 , wherein the primary and the secondary gates are connected so as to be able to receive a common voltage.

14. The thin film transistor of a flat panel display as claimed in claim 11 , wherein the doped regions are letter U shaped prongs connected in the middle.

15. The thin film transistor of a flat panel display as claimed in claim 11 , wherein the thin film transistor is able to switch a pixel that is included in the flat panel display.

16. A method of fabricating a thin film transistor of a flat panel display, comprising:

forming a semiconductor layer having doped regions and a channel region positioned between the doped regions;

forming a gate insulating layer on the semiconductor layer; and

forming a gate structure on the gate insulating layer and including a primary gate and a secondary gate, the primary gate being formed over the doped regions and across the channel region to switch the thin film transistor, and the secondary gate being formed over the channel region to switch the thin film transistor if a short circuit is formed between the doped regions.

17. The method of fabricating the thin film transistor of a flat panel display as claimed in claim 16 , wherein the forming of the gate structure includes forming a gate electrode, including a first portion of the gate electrode extending over the doped regions and across the channel region to be the primary gate, and a second portion of the gate electrode extending from the first portion to be the secondary gate.

18. The method of fabricating the thin film transistor of a flat panel display as claimed in claim 16 , wherein the forming of the gate structure includes forming the primary and the secondary gates to be connected so as to be able to receive a common voltage.

19. The method of fabricating the thin film transistor of a flat panel display as claimed in claim 16 , wherein forming of the semiconductor layer includes forming doped regions that are letter U shaped prongs connected in the middle.

20. The method of fabricating the thin film transistor of a flat panel display as claimed in claim 16 , wherein the thin film transistor is formed to be able to switch a pixel that is included in the flat panel display.