Method of manufacturing semiconductor integrated circuit
View Patent ↗A method of manufacturing a semiconductor integrated circuit including a logic part and a memory array part, the logic part having N-type and P-type FETs, and the memory array part having N-type and P-type FETs, includes the steps of forming N-type and P-type FETs constituting the logic part and the memory array part, thereafter sequentially forming a first insulation film having a tensile stress and a second insulation film on the whole surface, selectively removing the second insulation film and the first insulation film present on the upper side of the region of the P-type FET constituting the logic part, then forming a third insulation film having a compressive stress on the whole surface, and thereafter selectively removing the third insulation film present on the upper side of the region of the N-type FET constituting the logic part and the third insulation film present on the upper side of the regions of the N-type and P-type FETs constituting the memory array part.
1. A method of manufacturing a semiconductor integrated circuit comprising a logic part and a memory array part, said logic part comprised of an N channel type field effect transistor and a P channel type field effect transistor, and said memory array part comprised of an N channel type field effect transistor and a P channel type field effect transistor, said method comprising the following steps:
(A) forming gate parts, channel regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said logic part, and gate parts, channel regions and source/drain regions of said N channel type field effect transistor and said P channel type field effect transistor which constitute said memory array part, in a semiconductor substrate;
(B) forming a first insulation film having a tensile stress on a whole surface and forming a second insulation film on said first insulation film;
(C) selectively removing said second insulation film and said first insulation film present on an upper side of the region of said N channel type field effect transistor constituting said logic part;
(D) forming a third insulation film having a compressive stress on the whole surface; and
(E) selectively removing said third insulation film present on the upper side of the region of said P channel type field effect transistor constituting said logic part,
wherein between any two of said steps (B) to (D), ion implantation for relaxation of the compressive stress is applied to said first insulation film present on the region of said N channel type field effect transistor constituting said memory array part.
2. The method of manufacturing a semiconductor integrated circuit as set forth in claim 1 , wherein after said third insulation film having the tensile stress is formed, ion implantation for relaxation of the tensile stress is applied to said third insulation film present on the upper side of the region of said P channel type field effect transistor constituting said memory array part.
3. The method of manufacturing a semiconductor integrated circuit as set forth in claim 1 , wherein said first insulation film and said third insulation film are each comprised of a silicon nitride film, and said second insulation film is comprised of a silicon oxide film.