High voltage gate driver integrated circuit including high voltage junction capacitor and high voltage LDMOS transistor
View Patent ↗There is provided a high voltage gate driver integrated circuit. The high voltage gate driver integrated circuit includes: a high voltage region; a junction termination region surrounding the high voltage region; a low voltage region surrounding the junction termination region; a level shift transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region; and/or a high voltage junction capacitor disposed between the high voltage region and the low voltage region, at least some portions of the high voltage junction capacitor being overlapped with the junction termination region.
1. A high voltage gate driver integrated circuit comprising:
a high voltage region;
a junction termination region surrounding the high voltage region;
a low voltage region surrounding the junction termination region; and
a level shift transistor disposed between the high voltage region and the low voltage region, at least some portions of the level shift transistor being overlapped with the junction termination region;
wherein the level shift transistor is a LDMOS transistor and comprises:
a second conductive type epitaxial layer formed on a first conductive type substrate;
a first conductive type well region formed over the epitaxial layer;
a second conductive type highly doped source region formed over the well region;
a second conductive type highly doped drain region formed over the epitaxial layer to be separated from the well region in a lateral direction;
a gate electrode formed on a channel formation region over the well region through a gate insulating layer;
a source electrode electrically connected to the highly doped source region; and
a drain electrode electrically connected to the highly doped drain region.
2. The high voltage gate driver integrated circuit according to claim 1 , wherein the junction termination region comprises:
a first region separated from the high voltage region, the first region surrounding the high voltage region; and
a second region disposed between the first region and the high voltage region.
3. The high voltage gate driver integrated circuit according to claim 2 , wherein the first region comprises an insulating region electrically isolating the LDMOS transistor from the low voltage region, and wherein the insulating region is contacted to a lower portion of the well region and extends in a vertical direction to the substrate.
4. The high voltage gate driver integrated circuit according to claim 1 , further comprising a first conductive type highly doped contact region formed over the well region to be contacted to the source electrode.
5. The high voltage gate driver integrated circuit according to claim 4 , wherein the junction termination region comprises:
a first region separated from the high voltage region, the first region surrounding the high voltage region; and
a second region disposed between the first region and the high voltage region.
6. The high voltage gate driver integrated circuit according to claim 5 , wherein the first region comprises an insulating region electrically isolating the LDMOS transistor from the low voltage region, and wherein the insulating region is contacted to a lower portion of the well region and extends in a vertical direction to the substrate.