Buffered crossbar switch

1. A buffered crossbar switch having at least one mode of operation with a specific data packet size (L), said buffered crossbar switch comprising:

at least one queuing buffer having queuing buffer entries;

the mode of operation changing the size (E) or number (M) of said queuing buffer entries;

a plurality (R) of crossbar switches for operation in parallel; and

an expansion mode of operation operating said plurality (R) of crossbar switches in parallel and changing the queuing buffer entry size (E) to a fraction (L′=L/R) of said data packet size (L).

2. The buffered crossbar switch according to claim 1 , further comprising the mode of operation changing said size (E) of queuing buffer entries to said data packet size (L).

3. The buffered crossbar switch according to claim 1 further comprising:

the mode of operation choosing the memory size of said queuing buffer to be large enough to store M=M_min queuing buffer entries each having a length of L=L_max, wherein M_min is the minimum number of queuing buffer entries necessary for the mode of operation characterized by the largest data packet size, L_max.

4. The buffered crossbar switch according to claim 1 wherein said crossbar switch comprises 32 input ports (i 1 , . . . , i 32 ) or 32 output ports (o 1 , . . . , o 32 ).

5. The buffered crossbar switch according to claim 1 wherein said queuing buffer comprises 16 queuing buffer entries of 80 bytes in a first mode of operation, and said queuing buffer comprises 32 queuing buffer entries of 40 bytes in a second mode of operation, and said queuing buffer comprises 64 queuing buffer entries of 20 bytes in a third mode of operation.

6. The buffered crossbar switch according to claim 5 , wherein said first mode of operation is a single chip operation mode, wherein said second mode of operation is an expansion mode with two crossbar switches working in parallel, and wherein said third mode of operation is an expansion mode with four crossbar switches working in parallel.