Granted Patent B2

US 7,721,176 · App. 11/951,431 · Granted May 18, 2010

Abstract

Claims (53)

1. A method for integrated circuit recovery testing using simulation checkpoints, the method comprising:

executing an error injection test on an integrated circuit that includes a plurality of domains and latches, the error injection test including injecting an error into one of the domains, clock stopping the domain with the error, performing fencing between the domain with the error and the other domains, and quiescing the other domains;

creating a checkpoint of a state of the integrated circuit after the clock stopping, fencing and quiescing have been completed;

executing a mainline test of the integrated circuit, the mainline test including:

applying the checkpoint to the integrated circuit; and

performing a recovery reset of the stopped domain;

determining if the mainline test executed correctly; and

outputting the results of the determining.

2. The method of claim 1 further comprising performing a power on reset of the integrated circuit prior to executing the error injection test.

3. The method of claim 2 wherein the power on reset includes:

randomizing the latches in the plurality of domains;

resetting the latches; and

verifying that the latches were reset properly.

4. The method of claim 1 further comprising performing normal operations of the integrate circuit prior to executing the error injection test.

5. The method of claim 1 wherein the checkpoint includes the state of the latches on the integrated circuit.

6. The method of claim 1 wherein the method is performed by a simulation tool interfacing to the integrated circuit.

7. The method of claim 1 wherein the determining is performed by comparing actual results of the mainline test to expected results of the mainline test.

8. A system for integrated circuit recovery testing using simulation checkpoints, the system comprising:

a host system executing a simulation tool, the simulation tool facilitating:

executing an error injection test on an integrated circuit that includes a plurality of domains and latches, the error injection test including injecting an error into one of the domains, clock stopping the domain with the error, performing fencing between the domain with the error and the other domains, and quiescing the other domains;

creating a checkpoint of a state of the integrated circuit after the clock stopping, fencing and quiescing have been completed;

executing a mainline test of the integrated circuit, the mainline test including:

applying the checkpoint to the integrated circuit; and

performing a recovery reset of the stopped domain;

determining if the mainline test executed correctly; and

outputting the results of the determining; and

a data storage device storing the checkpoint.

9. The system of claim 8 wherein the simulation tool further facilitates performing a power on reset of the integrated circuit prior to executing the error injection test.

10. The system of claim 9 wherein the power on reset includes:

randomizing the latches in the plurality of domains;

resetting the latches; and

verifying that the latches were reset properly.

11. The system of claim 8 wherein the simulation tool further facilitates performing normal operations of the integrate circuit prior to executing the error injection test.

12. The system of claim 8 wherein the checkpoint includes the state of the latches on the integrated circuit.

13. The system of claim 8 wherein the simulation tool interfaces to the integrated circuit.

14. The system of claim 8 wherein the determining is performed by comparing actual results of the mainline test to expected results of the mainline test.

15. A computer program product for integrated circuit recovery testing using simulation checkpoints, the computer program product comprising:

a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for implementing a method, the method comprising:

executing an error injection test on an integrated circuit that includes a plurality of domains and latches, the error injection test including injecting an error into one of the domains, clock stopping the domain with the error, performing fencing between the domain with the error and the other domains, and quiescing the other domains;

creating a checkpoint of a state of the integrated circuit after the clock stopping, fencing and quiescing have been completed;

executing a mainline test of the integrated circuit, the mainline test including:

applying the checkpoint to the integrated circuit; and

performing a recovery reset of the stopped domain;

determining if the mainline test executed correctly; and

outputting the results of the determining.

16. The computer program product of claim 15 wherein the method further comprises performing a power on reset of the integrated circuit prior to executing the error injection test.

17. The computer program product of claim 16 wherein the power on reset includes:

randomizing the latches in the plurality of domains;

resetting the latches; and

verifying that the latches were reset properly.

18. The computer program product of claim 15 wherein the method further comprises performing normal operations of the integrate circuit prior to executing the error injection test.

19. The computer program product of claim 15 wherein the checkpoint includes the state of the latches on the integrated circuit.

20. The computer program product of claim 15 wherein the method is performed by a simulation tool interfaces to the integrated circuit.

Assignments (8)