Data holding circuit and signal processing circuit

1. A data holding circuit comprising:

two flip-flops and four exclusive OR circuits,

wherein

input ends of a first exclusive OR circuit receive an input signal and an output signal from a fourth exclusive OR circuit, respectively,

input ends of a second exclusive circuit receive an output signal from the first exclusive OR circuit and an output signal from a first flip-flip, respectively,

input ends of a third exclusive OR circuit receive the output signal from the first exclusive OR circuit and an output signal from a second flip-flop, respectively;

an input terminal of the first flip-flop receives an output signal from the second exclusive OR circuit and a clock terminal of the first flip-flop receives a clock signal, and the first flip-flop outputs input data that is input to the input terminal thereof from an output terminal thereof at a rising edge timing of the clock signal while holding the input data therein;

an input terminal of the second flip-flop receives an output signal from the third exclusive OR circuit, a clock terminal of the second flip-flop receives an inverted signal of the clock signal, and the second flip-flop outputs input data that is input to the input terminal thereof from an output terminal thereof at a falling edge timing of the clock signal while holding the input data therein, and

input ends of the fourth exclusive OR circuit receive the output signals from the first flip-flop and the second flip-flop, respectively, an output signal from the fourth exclusive OR circuit is output as an output result, and the input signal is latched at both the rising edge timing and the falling edge timing of the clock signal.

2. The data holding circuit according to claim 1 , wherein the first flip-flop and the second flip-flop are each provided with an asynchronous reset terminal, and a reset signal is input to each of the reset terminals of the respective first flip-flop and second flip-flop, so that a final output signal can be reset to ‘0’ by the reset signal.

3. The data holding circuit according to claim 1 , wherein the first flip-flop and the second flip-flop are each provided with an asynchronous set terminal, and a reset signal is input to each of the set terminals of the respective first flip-flop and second flip-flop, so that a final output signal can be reset to ‘0’ by the reset signal.

4. The data holding circuit according to claim 1 , wherein the first flip-flop is provided with an asynchronous set terminal, the second flip-flop is provided with an asynchronous reset terminal, and a set signal is input to the set terminal of the first flip-flop and the reset terminal of the second flip-flop, so that a final output signal can be set to ‘1’ by the set signal.

5. The data holding circuit according to claim 1 , wherein the first flip-flop is provided with an asynchronous reset terminal, the second flip-flop is provided with an asynchronous set terminal, and a set signal is input to the reset terminal of the first flip-flop and the set terminal of the second flip-flop, so that a final output signal can be set to ‘1’ by the set signal.

6. The data holding circuit according to claim 1 , wherein the first flip-flop is provided with an asynchronous reset terminal and an asynchronous set terminal, the second flip-flop is provided with an asynchronous reset terminal, a reset signal is input to the reset terminal of the first flip-flop, a set signal is input to the set terminal of the first flip-flop, and a signal obtained as a result of an AND operation with the reset signal and the set signal is input to the reset terminal of the second flip-flop, so that a final output signal can be reset to ‘0’ by the reset signal and the final output signal can be set to ‘1’ by the set signal.

7. The data holding circuit according to claim 1 , wherein the first flip-flop is provided with an asynchronous reset terminal, the second flip-flop is provided with an asynchronous reset terminal and an asynchronous set terminal, a reset signal is input to the reset terminal of the second flip-flop, a set signal is input to the set terminal of the second flip-flop, and a signal obtained as a result of an AND operation with the reset signal and the set signal is input to the reset terminal of the first flip-flop, so that a final output signal can be reset to ‘0’ by the reset signal and the final output signal can be set to ‘1’ by the set signal.

8. The data holding circuit according to claim 1 , wherein the first flip-flop is provided with an asynchronous reset terminal and an asynchronous set terminal, the second flip-flop is provided with an asynchronous set terminal, a reset signal is input to the set terminal of the first flip-flop, a set signal is input to the reset terminal of the first flip-flop, and a signal obtained as a result of an AND operation with the reset signal and the set signal is input to the set terminal of the second flip-flop, so that a final output signal can be reset to ‘0’ by the reset signal and the final output signal can be set to ‘1’ by the set signal.

9. The data holding circuit according to claim 1 , wherein the first flip-flop is provided with an asynchronous set terminal, the second flip-flop is provided with an asynchronous reset terminal and an asynchronous set terminal, a reset signal is input to the set terminal of the second flip-flop, a set signal is input to the reset terminal of the second flip-flop, and a signal obtained as a result of an AND operation with the reset signal and the set signal is input to the set terminal of the first flip-flop, so that a final output signal can be reset to ‘0’ by the reset signal and the final output signal can be set to ‘1’ by the set signal.

10. The data holding circuit according to claim 1 , wherein the first flip-flop latches an input signal to the first flip-flop at the rising edge timing of the clock signal, and the second flip-flop latches an input signal to the second flip-flop at the falling edge timing of the clock signal.

11. A signal processing circuit comprising:

a first flip-flop for outputting input data that is input to a data input terminal thereof from an output terminal thereof at a rising edge timing of a clock signal while holding the input data therein;

a second flip-flop for outputting input data that is input to a data input terminal thereof from an output terminal thereof at a falling edge timing of the clock signal while holding the data therein;

a combinational circuit for performing a predetermined computation on an output signal from the first flip-flop and an output signal from the second flip-flop; and

the data holding circuit according to claim 1 for receiving a computation result data from the combinational circuit and outputting a change point detection signal.

12. A signal processing circuit comprising:

a first flip-flop for outputting input data that is input to a data input terminal thereof from an output terminal thereof at a rising edge timing of a clock signal while holding the input data therein;

a second flip-flop for outputting input data that is input to a data input terminal thereof from an output terminal thereof at a falling edge timing of the clock signal while holding the input data therein;

the data holding circuit according to claim 1 for latching, as an input signal thereto, a signal obtained as a result of an exclusive OR operation with an output signal from the first flip-flop and an output signal from the second flip-flop;

one adding circuit for adding 1 to an output signal from the data holding circuit or clear the output signal by setting the output signal to 0 in accordance with a level of the change point detection signal; and

a second plurality of data holding circuits according to claim 1 for each latching a computation result data from the one adding circuit as an input signal thereto,

wherein

an output signal from each of the second plurality of data holding circuits configures a counter as an input signal to the one adding circuit, so that ‘0’ period or ‘1’ period of the input signal can be counted at every half-clock cycle.

13. A signal processing circuit comprising:

a signal selection output circuit including one or a plurality of frequency-dividing circuits for frequency-dividing an original oscillation clock signal, a selection circuit for selecting a desired clock signal among the original oscillation clock signal and the frequency-divided clock signals, and a signal output circuit for outputting the selected clock signal; and

the data holding circuit according to claim 1 for latching a clock signal from the signal selection output circuit as an input signal thereto.