Processor and data processing system employing a variable store gather window

1. A processor, comprising:

at least one instruction execution unit that executes store instructions to obtain store operations;

a store queue coupled to said instruction execution unit, said store queue including:

a queue entry in which said store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory, wherein a gather indication is generated when a store operation is gathered in the queue entry; and

dispatch logic that varies a duration of said store gathering window, wherein said dispatch logic includes:

a counter that increments during clock cycles in which the gather indication is not asserted;

selection circuitry that selects a store gathering window duration for said queue entry;

a policy control unit that controls selection by said selection circuitry; and

a comparator that compares a count of said counter and said store gathering window duration, and responsive thereto, generates a dispatch signal to cause dispatch of a write transaction from said queue entry.

2. The processor of claim 1 , wherein said duration of the store gathering window comprises a selected number of clock cycles.

3. The processor of claim 1 , wherein:

said queue entry comprises a first queue entry;

said store gathering window is a first store gathering window;

said store queue includes a second queue entry; and

said dispatch logic applies a second store gathering window of different duration to said second queue entry.

4. The processor of claim 1 , wherein:

said store queue includes a plurality of queue entries including said queue entry; and

said store queue further comprises queue allocation logic that allocates said plurality of queue entries to store operations.

5. The processor of claim 1 , and further comprising one or more levels of cache memory.

6. A data processing system, comprising:

an interconnect;

a memory coupled to said interconnect; and

a processor coupled to said interconnect, said processor including:

at least one instruction execution unit that executes store instructions to obtain store operations;

a store queue coupled to said instruction execution unit, said store queue including:

a queue entry in which said store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to memory, wherein a gather indication is generated when a store operation is gathered in the queue entry; and

dispatch logic that varies a duration of said store gathering window, wherein said dispatch logic includes:

a counter that increments during clock cycles in which the gather indication is not asserted;

selection circuitry that selects a store gathering window duration for said queue entry;

a policy control unit that controls selection by said selection circuitry; and

a comparator that compares a count of said counter and said store gathering window duration, and responsive thereto, generates a dispatch signal to cause dispatch of a write transaction from said queue entry.

7. The data processing system of claim 6 , wherein said duration of the store gathering window comprises a selected number of clock cycles.

8. The data processing system of claim 6 , wherein:

said queue entry comprises a first queue entry;

said store gathering window is a first store gathering window;

said store queue includes a second queue entry; and

said dispatch logic applies a second store gathering window of different duration to said second queue entry.