Thin film transistors in pixel and driver portions characterized by surface roughness
View Patent ↗A thin film transistor and a fabrication method thereof, in which one excimer laser annealing (ELA) makes a pixel portion and a driver portion different from each other in surface roughness and grain size. The thin film transistor includes: a substrate including a pixel portion and a driver portion; a first semiconductor layer disposed in the pixel portion and having a first surface roughness; a second semiconductor layer disposed in the driver portion and having a second surface roughness smaller than the first surface roughness; a gate insulating layer formed on the substrate including the first and second semiconductor layers; a first gate electrode placed to correspond to the first semiconductor layer on the gate insulating layer; a second gate electrode placed to correspond to the second semiconductor layer on the gate insulating layer; an interlayer insulating layer formed on the substrate including the first and second gate electrodes; first source and drain electrodes formed on the interlayer insulating layer and electrically connected with the first semiconductor layer; and second source and drain electrodes formed on the interlayer insulating layer and electrically connected with the second semiconductor layer.
1. A thin film transistor comprising:
a substrate including a pixel portion and a driver portion;
a first semiconductor layer disposed in the pixel portion and having a first surface roughness;
a second semiconductor layer disposed in the driver portion and having a second surface roughness larger than the first surface roughness, wherein the first semiconductor layer and the second semiconductor layer are disposed on the same substrate;
a first gate electrode disposed to correspond to the first semiconductor layer;
a second gate electrode disposed to correspond to the second semiconductor layer;
a gate insulating layer disposed between the first and second semiconductor layers and the first and second gate electrodes;
first source and drain electrodes electrically connected to source and drain regions of the first semiconductor layer; and
second source and drain electrodes electrically connected to source and drain regions of the second semiconductor layer, wherein,
a root mean square (RMS) ratio of the first surface roughness to the second surface roughness is 25˜90%, and
the first surface roughness is 18-270 Å.
2. The thin film transistor according to claim 1 , wherein the second surface roughness is 20-300 Å.
3. The thin film transistor according to claim 1 , wherein the first and second gate electrodes include a molybdenum-tungsten (MoW) alloy.