Semiconductor device having EDMOS transistor and method for manufacturing the same
View Patent ↗A semiconductor device having an EDMOS transistor and a method for forming the same are provided. The semiconductor device includes source and drain regions formed separately in a semiconductor substrate, a first gate insulating layer filling a trench formed in the substrate between the source and drain regions, the first gate insulating layer being adjacent to the drain region and separated from the source region, a second gate insulating layer formed over the substrate between the first gate insulating layer and the source region, the second gate insulating layer being thinner than the first gate insulating layer, a gate electrode formed over the first and second gate insulating layers, and a doped drift region formed in the substrate under the first gate insulating layer, the doped drift region being in contact with the drain region. This reduces the planar area of the EDMOS transistor, thereby achieving highly integrated semiconductor devices.
1. A method comprising:
forming a trench in a specific region of a semiconductor substrate using a hard mask pattern formed on the semiconductor substrate as an etch mask, wherein the trench is formed from a top surface of the semiconductor substrate to a maximum depth of about 2000 Å to about 8000 Å;
forming a first gate insulating layer which fills the trench;
forming a doped drift region in the semiconductor substrate under the first gate insulating layer;
forming a source region and a drain region in the semiconductor substrate at both sides of the first gate insulating layer, the source region being separated from the first gate insulating layer and the drain region being in contact with the doped drift region;
forming a second gate insulating layer over the semiconductor substrate between the first gate insulating layer and the source region, wherein the doped drift region is separate from the second gate insulating layer; and
forming a gate electrode over the first and second gate insulating layers,
wherein said forming a first gate insulating layer comprises:
forming an insulating layer formed over the semiconductor substrate to fill the trench;
planarizing the insulating layer until the hard mask pattern is exposed; and
etching an upper portion of the first gate insulating layer when removing the hard mask pattern.
2. The method of claim 1 , wherein the trench is formed in a rounded shape.
3. The method of claim 1 , wherein the gate electrode is formed to cover only a portion of the first gate insulating layer which is adjacent to the second gate insulating layer.
4. The method of claim 1 , wherein the doped drift region is formed to have a lower impurity concentration than the drain region.
5. The method of claim 1 , wherein the second gate insulating layer is thinner than the first gate insulating layer.