SEMICONDUCTOR MEMORY DEVICE
The present invention provides a semiconductor memory device capable of allocating scrambling data different every chip without the need for management and writing of seed data for scramble. If an authentication key inputted from a user to an authentication key register and a decision key set to a decision key register in advance coincide with each other, then read data RD read from a memory chip is outputted as data DT via a selector as it is. If they are found not to coincide with each other, then read data RD (scrambled data SRD) scrambled using, as seed data SD, position information on each defective memory cell, which is outputted from a fuse circuit, is selected by the selector, followed by being outputted as data DT.
1 . A semiconductor memory device which compares an authentication key inputted from a user and a preset decision key and which outputs data stored in a semiconductor memory as it is when they coincide with each other and scrambles the data when they are inconsistent with each other and outputs the so-scrambled data, said semiconductor memory device comprising:
a scramble circuit for scrambling the data, which is configured so as to use information set to a fuse circuit as seed data for scramble.
2 . The semiconductor memory device according to claim 1 , wherein the fuse circuit holds information about a position of each defective memory cell in the semiconductor memory.
3 . The semiconductor memory device according to claim 1 or 2 , wherein the scramble circuit calculates exclusive ORing of the data stored in the semiconductor memory and the seed data every bit and outputs a result of exclusive ORing therefrom.
4 . The semiconductor memory device according to claim 1 or 2 , wherein the scramble circuit includes:
a first register which sets the seed data as an initial value,
a second register which sets an undefined value at power-on as an initial value,
a first bit manipulation unit which rearranges the order of bits of data outputted from the first register,
a second bit manipulation unit which rearranges the order of bits of data outputted from the second register,
a first exclusive OR gate which exclusive-ORs the data outputted from the first bit manipulation unit and the data outputted from the second register every bit and outputs a result of exclusive ORing therefrom,
a second exclusive OR gate which exclusive-ORs the data outputted from the second bit manipulation unit and the data outputted from the first register every bit and outputs a result of exclusive ORing therefrom,
a selector which switches the data outputted from the first or second register in accordance with an address signal, and
a third exclusive OR gate which exclusive-ORs the data outputted from the selector and the data read from the semiconductor memory every bit,
wherein the output of the first exclusive OR gate is fetched into the first register at a timing of fall of the address signal, and the output of the second exclusive OR gate is fetched into the second register at a timing of rise of address signal.