Semiconductor structure and fabricating method thereof for liquid crystal display device
A method for fabricating a semiconductor structure with a multi-layer storage capacitor is provided. A substrate having an active element area and a storage capacitor area is provided. By sequentially fabricating a semiconductor layer, a first inter-layer dielectric (ILD) layer, a gate and a first electrode, a source and a drain in the semiconductor layer in the active element area, a second ILD layer, a patterned conductive layer served as a pixel electrode, a patterned third ILD layer, a plurality of contact windows in the first, second and third ILD layers for exposing the source, the drain, parts of the patterned conductive layer and the first electrode, a second electrode and a source/drain conductive line, the semiconductor structure with the multi-layer storage is obtained in consequence.
1. A method for fabricating a semiconductor structure, comprising:
forming a semiconductor layer on a substrate, the semiconductor layer disposed in an active element area and a storage capacitor area of the substrate;
forming a first inter-layer dielectric layer to cover the semiconductor layer;
forming a gate on the first inter-layer dielectric layer in the active element area and a first electrode on the first inter-layer dielectric layer in a storage capacitor area;
performing a doping process to form a source and a drain in the semiconductor layer in the active element area, and a channel is between the source and the drain;
forming a second inter-layer dielectric layer to cover the gate and the first electrode;
forming a patterned conductive layer on the second inter-layer dielectric layer as a pixel electrode;
forming a third inter-layer dielectric layer to cover the patterned conductive layer;
patterning the third inter-layer dielectric layer to expose the patterned conductive layer and forming a plurality of contact windows in the first, second and third inter-layer dielectric layers to expose the source, the drain, a portion of the patterned conductive layer and the first electrode; and
forming a second electrode on the third inter-layer dielectric layer disposed over the first electrode and electrically connected to the first electrode, and a source/drain conductive line electrically connecting the semiconductor layer with the patterned conductive layer.
2. The method for fabricating the semiconductor structure as claimed in claim 1 , wherein the semiconductor layer and the patterned conductive layer are electrically coupled as a first capacitor electrode, and the first electrode and the second electrode are electrically coupled as a second capacitor electrode.
3. The method for fabricating the semiconductor structure as claimed in claim 2 , wherein the first capacitor electrode and the second electrode constitute a storage capacitor.
4. The method for fabricating the semiconductor structure as claimed in claim 1 , further comprising forming a patterned protective layer on the second electrode and the source/drain conductive line.
5. The method for fabricating the semiconductor structure as claimed in claim 1 , further comprising forming a lightly doped drain area disposed between the source and the channel and between the drain and the channel.
6. The method for fabricating the semiconductor structure as claimed in claim 1 , wherein the material of the semiconductor layer comprises poly-silicon.
7. The method for fabricating the semiconductor structure as claimed in claim 1 , wherein the materials of the gate and the first electrode are selected from molybdenum (Mo), tungsten molybdenum (MoW), chromium (Cr), titanium (Ti), aluminum (Al), copper (Cu) and a combination of the aforementioned.
8. The method for fabricating the semiconductor structure as claimed in claim 1 , wherein the material of the patterned conductive layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO).
9. The method for fabricating the semiconductor structure as claimed in claim 1 , wherein the second electrode and the source/drain conductive line comprise a multi-layer metal structure constituted by titanium-aluminum-titanium (Ti—Al—Ti) or molybdenum-aluminum-molybdenum (Mo—Al—Mo).
10. The method for fabricating the semiconductor structure as claimed in claim 1 , wherein the materials of the first inter-layer dielectric layer, the second inter-layer dielectric layer and the third inter-layer dielectric layer are selected from silicon nitride, silicon oxide, silicon oxynitride and a combination thereof.
11. A semiconductor structure, comprising:
a semiconductor layer, disposed on an active element area and a storage capacitor area of a substrate, the semiconductor layer in the active element area comprising a source, a drain and a channel disposed between the source and the drain;
a first inter-layer dielectric layer, covering the semiconductor layer;
a gate and a first electrode, the gate disposed on the first inter-layer dielectric layer in the active element area, the first electrode disposed on the first inter-layer dielectric layer in the storage capacitor area, and the gate, the source and the drain constituting an active element;
a second inter-layer dielectric layer, covering the gate and the first electrode;
a patterned conductive layer, disposed on the second inter-layer dielectric layer and serving as a pixel electrode;
a third inter-layer dielectric layer, covering the patterned conductive layer;
a plurality of contact windows, disposed in the first, second and third inter-layer dielectric layers so as to expose the patterned conductive layer, the source, the drain and the first electrode; and
a second electrode and a source/drain conductive line, disposed on the third inter-layer dielectric layer, the second electrode disposed over the first electrode and electrically connected to the first electrode, the source/drain conductive line electrically connecting the semiconductor layer with the patterned conductive layer.
12. The semiconductor structure as claimed in claim 11 , wherein the semiconductor layer and the patterned conductive layer are electrically coupled as a first capacitor electrode, and the first electrode and the second electrode are electrically coupled as a second capacitor electrode.
13. The semiconductor structure as claimed in claim 12 , wherein the first capacitor electrode and the second capacitor electrode constitute a storage capacitor.
14. The semiconductor structure as claimed in claim 11 , further comprising a patterned protective layer covering the second electrode and the source/drain conductive line.
15. The semiconductor structure as claimed in claim 14 , wherein the patterned conductive layer further comprises a contact pad disposed on the periphery of the substrate so as to electrically connect the active element to other electronic elements.
16. The semiconductor structure as claimed in claim 11 , further comprising a lightly doped drain area disposed between the source and the channel and between the drain and the channel.
17. The semiconductor structure as claimed in claim 11 , wherein the material of the semiconductor layer comprises poly-silicon.
18. The semiconductor structure as claimed in claim 11 , wherein the material of the patterned conductive layer comprises indium tin oxide (ITO) or indium zinc oxide (IZO).
19. The semiconductor structure as claimed in claim 11 , wherein the second electrode and the source/drain conductive line comprise a multi-layer metal structure constituted by titanium-aluminum-titanium (Ti—Al—Ti) or molybdenum-aluminum-molybdenum (Mo—Al—Mo).
20. The semiconductor structure as claimed in claim 11 , wherein the materials of the first inter-layer dielectric layer, the second inter-layer dielectric layer and the third inter-layer dielectric layer are selected from silicon nitride, silicon oxide, silicon oxynitride and a combination thereof.
21. A pixel structure, suitable for being disposed on a substrate, comprising:
an active element; and
a multi-layer storage capacitor, electrically connected to the active element, the multi-layer storage capacitor comprising:
a semiconductor layer, disposed on the substrate;
a first electrode, disposed over the semiconductor layer;
a pixel electrode, disposed over the first electrode;
a second electrode, disposed over the pixel electrode;
wherein the semiconductor layer and the pixel electrode are electrically coupled as a first capacitor electrode, the first electrode and the second electrode are electrically coupled as a second capacitor electrode, and the first capacitor electrode and the second capacitor electrode constitute the multi-layer storage capacitor.
22. The pixel structure as claimed in claim 21 , wherein the active element comprises a low temperature poly-silicon thin film transistor (LTPS-TFT).
23. A liquid crystal display (LCD) panel, comprising:
a thin film transistor (TFT) array substrate comprising a plurality of pixel structures, wherein each of the pixel structures comprises:
an active element; and
a multi-layer storage capacitor, electrically connected to the active element,
the multi-layer storage capacitor comprising:
a semiconductor layer, disposed on the TFT array substrate;
a first electrode, disposed over the semiconductor layer;
a pixel electrode, disposed over the first electrode;
a second electrode, disposed over the pixel electrode;
wherein the semiconductor layer and the pixel electrode are electrically coupled as a first capacitor electrode, the first electrode and the second electrode are electrically coupled as a second capacitor electrode, and the first capacitor electrode and the second capacitor electrode constitute the multi-layer storage capacitor;
a color filter substrate, disposed opposite to the TFT array substrate; and
a liquid crystal layer, disposed between the TFT array substrate and the color filter substrate.
24. The LCD panel as claimed in claim 23 , wherein the color filter substrate comprises:
a substrate;
a color filter layer, disposed on the substrate; and
a common electrode, disposed on the color filter layer and opposite to the pixel electrode.