TFT array substrate and manufacturing method thereof
View Patent ↗A TFT array substrate and a manufacturing method thereof, where the TFT array substrate includes a substrate; a gate line and a gate electrode integrated therewith, which are covered by a gate insulating layer, a semiconductor layer, and a ohmic contact layer sequentially. An insulating layer is formed on the resulting substrate and on both sides of the gate line and the gate electrode, the gate insulating layer, the semiconductor layer, and the ohmic contact layer. A trench is then formed in the ohmic contact layer to divide the ohmic contact layer over the semiconductor layer. A data line and first and second source/drain electrodes are then formed on the insulating layer and the ohmic contact layer.
1. A method of manufacturing a thin film transistor (TFT) array substrate, comprising the following steps performed in the order presented:
(a) forming stacked layers of a gate metal layer, a gate insulating layer, a semiconductor layer, and an ohmic contact layer sequentially on a substrate, and then patterning the stacked layers of the gate metal layer, the gate insulating layer, the semiconductor layer, and the ohmic contact layer to form a pattern of a gate line and a gate electrode;
(b) forming an insulating layer on the resulting substrate of step (a), a thickness of which is greater than a total thickness of the gate metal layer, the gate insulating layer, the semiconductor layer, and the ohmic contact layer, and thinning the insulating layer partially to expose the ohmic contact layer;
(c) forming and patterning a source/drain metal layer on the resulting substrate of step (b) to form first and second source/drain electrodes and a data line and to expose the ohmic contact layer between the first and second source/drain electrodes, and patterning the exposed ohmic contact layer to form a trench that divides the ohmic contact layer, the first and second source/drain electrodes opposing to each other with respect to the trench;
(d) forming and patterning a passivation layer on the resulting substrate to form a via hole in the passivation layer over the second source/drain electrode; and
(e) forming and patterning a pixel electrode layer on the resulting substrate to form a pixel electrode that is connected with the second source/drain electrode through the via hole.
2. The method according to claim 1 , wherein in the step (a), the sequential forming of the gate metal layer, the gate insulating layer, the semiconductor layer, and the ohmic contact layer on the resulting substrate is performed continuously.
3. The method according to claim 1 , wherein in the step (a), the gate line and the gate electrode are formed by etching the gate metal layer, the insulating layer, the semiconductor layer, and the ohmic contact layer with a multi-step etching.
4. The method according to claim 1 , wherein in the step (b), the insulating layer is an organic insulating layer.
5. The method according to claim 4 , wherein the organic insulating layer is coated by a spin coating method.
6. The method according to claim 4 , wherein the organic insulating layer is formed of a material selected from the group consisting of epoxy resin, polyamine, pentacene, polyvinyl pyrrolidone, polyimide, and acryl resin.
7. The method according to claim 4 , wherein in the step (b), the thinning process is an oxygen reactive ion etching process in cooperation with an endpoint detector.
8. The method according to claim 4 , wherein in the step (b), after the organic insulating layer is thinned partially to expose the ohmic contact layer, a top surface of the organic insulating layer is flush with a top surface of the ohmic contact layer to form a substantially flat surface.
9. The method according to claim 1 , wherein in the step (b), after the insulating layer is partially thinned to expose the ohmic contact layer, the top surface of the insulating layer is flush with the top surface of the ohmic contact layer to form a substantially flat surface.