Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same
View Patent ↗A semiconductor device comprises a first transistor having a composite gate structure containing a lamination of a first polycrystalline silicon film, an interlayer insulating film, and a second polycrystalline silicon film; and a second transistor having a single gate structure containing a lamination of a third polycrystalline silicon film and a fourth polycrystalline silicon film, wherein the first polycrystalline silicon film and the third polycrystalline silicon film have substantially the same thickness; the first polycrystalline silicon film and the third polycrystalline silicon film have different impurity concentrations controlled independently of each other; the second polycrystalline silicon film and the fourth polycrystalline silicon film have substantially the same thickness, and the second polycrystalline silicon film, the fourth polycrystalline silicon film, and the third polycrystalline silicon film have substantially the same impurity concentration. Also, a method for manufacturing the above-described semiconductor device is described.
1. A method of manufacturing a semiconductor device having a first region and a second region, the method comprising:
forming a first oxide film on a substrate in the first region;
forming a second oxide film on the substrate in the second region;
forming a first conductive layer over a portion of the substrate that includes at least the first oxide film and the second oxide film;
introducing impurities into the first conductive layer;
forming a first insulating layer over the first conductive layer;
removing at least a portion of the first insulating layer over the second region;
forming a second conductive layer over at least a portion of the substrate such that the first and second conductive layers are separated by the first insulating layer in the first region and the first and second conductive layers are at least partially in contact with each other over their cross-sections in the second region; and
introducing impurities into the second conductive layer such that the second conductive layer has a conductivity that is higher than the first conductive layer in the first region, and such that the first and second conductive layers have substantially the same conductivity in the second region.
2. The method of claim 1 , further comprising patterning the first region to form a memory cell transistor and patterning the second region to form a peripheral transistor.
3. The method of claim 1 , further comprising removing substantially all of the first insulating layer over the second region.
4. The method of claim 1 , further comprising removing only a portion of the first insulating layer over the second region.
5. The method of claim 1 , further comprising forming a field oxide film on the substrate to provide element isolation regions that surround the first and second regions.
6. The method of claim 1 , wherein the first oxide film is a tunnel oxide film formed by thermal oxidation.
7. The method of claim 1 , wherein the second oxide film is a gate oxide film formed by thermal oxidation.
8. The method of claim 1 , wherein the impurities introduced into the first conductive layer are phosphorous or arsenic impurities.
9. The method of claim 1 , further comprising introducing the impurities into the first conductive layer by ion injection.
10. The method of claim 1 , further comprising introducing the impurities into the second conductive layer by vapor phase diffusion.
11. The method of claim 1 , wherein introducing the impurities into the first conductive layer and introducing the impurities into the second conductive layer is performed such that the second conductive layer has an impurity concentration at least 10 times that of the first conductive layer in the first region.
12. A method of manufacturing a semiconductor device having a first region and a second region, the method comprising:
forming a first oxide film on a substrate in the first region;
forming a second oxide film on the substrate in the second region;
forming a first conductive layer over a portion of the substrate that includes at least the first region and the second region;
introducing impurities into the first conductive layer;
forming a first insulating layer over the first conductive layer;
removing at least a portion of the first insulating layer over the second region;
forming a second conductive layer over at least a portion of the substrate such that the first and second conductive layers are separated by the first insulating layer in the first region and the first and second conductive layers are at least partially in contact with each other over their cross-sections in the second region; and
introducing impurities into the second conductive layer such that the second conductive layer has a conductivity that is higher than the first conductive layer in the first region, and such that the first and second conductive layers have substantially the same conductivity in the second region.
13. The method of claim 12 , further comprising patterning the first region to form a memory cell transistor and patterning the second region to form a peripheral transistor.
14. The method of claim 12 wherein the first oxide film is a tunnel oxide film formed by thermal oxidation.
15. The method of claim 12 , wherein the second oxide film is a gate oxide film formed by thermal oxidation.
16. The method of claim 12 , wherein introducing the impurities into the first conductive layer and introducing the impurities into the second conductive layer is performed such that the second conductive layer has an impurity concentration at least 10 times that of the first conductive layer in the first region.
17. A method of manufacturing a semiconductor device having a first region and a second region, the method comprising:
forming a first conductive layer over a portion of a substrate that includes at least a first region and a second region, wherein the first and second regions are defined by a field oxide film formed on the substrate, the first region having a first oxide film formed thereon and the second region having a second oxide film formed thereon;
introducing impurities into the first conductive layer;
forming a first insulating layer over the first conductive layer;
removing at least a portion of the first insulating layer over the second region;
forming a second conductive layer over the first insulating layer and the first conductive layer such that the first and second conductive layers are separated by the first insulating layer in the first region and are at least partially in contact with each other in the second region; and
introducing impurities into the second conductive layer such that the second conductive layer has a conductivity that is higher than the first conductive layer in the first region, and such that the first and second conductive layers have substantially the same conductivity in the second region.
18. The method of claim 17 , further comprising patterning the first region to form a memory cell transistor and patterning the second region to form a peripheral transistor.
19. The method of claim 17 , wherein the first oxide film is a tunnel oxide film.
20. The method of claim 17 , wherein the second oxide film is a gate oxide film.
21. The method of claim 17 , wherein introducing the impurities into the first conductive layer and introducing the impurities into the second conductive layer is performed such that the second conductive layer has an impurity concentration at least 10 times that of the first conductive layer in the first region.