Method and apparatus for direct digital to radio frequency conversion
View Patent ↗A method and apparatus for direct conversion of digital data to high power RF signals, known as DDRF. The method and apparatus receive a digital signal, create a digital modulated signal therefrom, and amplify the modulated signal with an H-bridge Power Amplifier for transmission. DDRF uses a multi-level H-bridge amplification circuit to establish a more power efficient digital transmitter.
1. A digital to radio frequency amplifier system comprising:
a bandpass delta sigma modulator for receiving a modulated carrier input and for producing a multilevel modulation signal;
a level select logic mapper connected to receive said multilevel modulation signal, said level select logic mapper provides a plurality of drive signals; and
an H-bridge amplifier connected to said plurality of drive signals of said level select logic mapper wherein said H-bridge amplifier is driven by said level select logic mapper.
2. The digital to radio frequency amplifier system of claim 1 , further comprising a first bandpass filter connected between said H-bridge amplifier and a load.
3. The digital to radio frequency amplifier system of claim 1 , wherein said H-bridge amplifier is a half-bridge amplifier.
4. The digital to radio frequency amplifier system of claim 1 , wherein said H-bridge amplifier is a multi-level H-bridge amplifier that comprises:
a drain node of a first Field Effect Transistor (FET) connected to a first power supply;
a source node of a said first FET connected to a first load-end bandpass filter;
a gate node of said first FET connected to a first output of said level select logic mapper;
a second load-end bandpass filter connected to a source node of a second FET;
a drain node of said second FET connected to said first power supply;
a gate node of said second FET connected to a second output of said level select logic mapper;
a drain node of a third FET connected to said source node of said first FET;
a source node of said third FET connected to a second power supply;
a gate node of said third FET connected to a third output of said level select logic mapper;
a drain node of a fourth FET connected to said source node of said second FET;
a source node of said fourth FET connected to said second power supply; and
a gate node of said fourth FET connected to a fourth output of said level select logic mapper.
5. The digital to radio frequency amplifier system of claim 4 , wherein said multi-level modulation signal of said multilevel bandpass delta sigma modulator is a 3 level modulation signal.
6. The digital to radio frequency amplifier system of claim 4 , wherein said first FET, second FET, third FET, and fourth FET are each a gallium nitride FET.
7. The digital to radio frequency amplifier system of claim 4 , wherein the system is implemented using a MMIC process.
8. The digital to radio frequency amplifier system of claim 4 , wherein said multi-level H-bridge amplifier further comprises:
a drain node of a fifth FET connected to a third power supply;
a source node of a said fifth FET connected to said source node of said first FET;
a gate node of said fifth FET connected to a fifth output of said level select logic mapper;
a drain node of a sixth FET connected to said third power supply;
a source node of said sixth FET connected to said source node of said second FET; and
a gate node of said sixth FET connected to a sixth output of said level select logic mapper.
9. The digital to radio frequency amplifier system of claim 8 , wherein said multi-level modulation signal of said multilevel bandpass delta sigma modulator comprises one of a 4 level modulation signal and a 5 level modulation signal.
10. The digital to radio frequency amplifier system of claim 8 , where said first FET, second FET, third FET, fourth FET, fifth FET, and sixth FET are each a gallium nitride FET.
11. The device of claim 8 , wherein said multi-level H-bridge amplifier further comprises:
a drain node of a seventh FET connected to said source node of said first FET;
a source node of said seventh FET connected to a fourth power supply;
a gate node of said seventh FET connected to a seventh output of said level select logic mapper;
a drain node of a eighth FET connected to said source node of said second FET;
a source node of said eighth FET connected to said fourth power supply; and
a gate node of said eighth FET connected to an eighth output of said level select logic mapper.
12. The digital to radio frequency amplifier system of claim 11 , wherein said multi-level modulation signal of said multilevel bandpass delta sigma modulator comprises one of is a 4 level modulation signal and a 5 level modulation signal.
13. A method of directly converting a digital signal to a radio frequency and relaying the radio frequency, the method comprising:
receiving a modulated signal;
creating, by a bandpass delta sigma modulator, a multi-level modulated signal based on the received modulated signal;
mapping to an H-bridge power amplifier, the multi-level modulated signal through a level select logic mapper; and
providing an amplified digital-RF signal to a load.
14. The method of claim 13 , wherein the multi-level modulated signal is a 3 level modulated signal and wherein the H-bridge power amplifier comprises a 4 FET H-bridge power amplifier.
15. The method of claim 13 , wherein the 4-FET H-bridge power amplifier is a half-bridge amplifier.
16. The method of claim 13 , wherein the H-bridge power amplifier comprises a 6 FET H-bridge power amplifier.
17. The method of claim 16 , wherein the 6-FET H-bridge power amplifier is a half-bridge amplifier.
18. The method of claim 13 , wherein the H-bridge power amplifier comprises an 8 FET H-bridge power amplifier.
19. A Direct Digital to Radio Frequency (DDRF) system comprising:
a bandpass delta sigma modulator for receiving a modulated carrier input and for producing a multilevel modulation signal, wherein said multi-level modulation signal further comprises a zero state;
a level select logic mapper connected to receive said multilevel modulation signal, said level select logic mapper provides a plurality of drive signals; and
an H-bridge amplifier connected to said plurality of drive signals of said level select logic mapper wherein said H-bridge amplifier is driven by said level select logic mapper.
20. The DDRF system of claim 19 , wherein said H-bridge amplifier dissipates a stored energy by active commutation when said zero state is generated.