System for transmitting data between transmitter and receiver modules on a channel provided with a flow control link

1. A system for transmitting data in a network-on-chip (NoC) comprising:

a NoC transmitter module;

a NoC receiver module;

a channel between said NoC transmitter module and said NoC receiver module for providing

a first control signal from said NoC transmitter module to said NoC receiver module, and

a second control signal from said NoC receiver module to said NoC transmitter module for initiating data transmission; and

said NoC receiver module comprising a multi-stage buffer, and a controller cooperating therewith for synchronizing the first and second control signals, said multi-stage buffer comprising a first latch circuit for latching and delivering the first control signal in synchronization with a transmitter clock signal and being controlled by a first control driving signal based on the transmitter clock signal, and a second latch circuit for latching data provided by said first latch circuit, and delivering the data in synchronization with a receiver clock signal.

2. A system according to claim 1 , wherein said second latch circuit is controlled by a second control driving signal that is based on the receiver clock signal signals, with the respective first and second control driving signals being in synchronization with the transmitter and receiver clock signals.

3. A system according to claim 2 , wherein said first and second latch circuits are configured for alternately latching the first control signal in said first and second latch circuits.

4. A system according to claim 2 , wherein said first latch circuit is activated by a rising edge of the first control driving signal, and said second latch circuit is activated by a falling edge of the second control driving signal.

5. A system according to claim 1 , wherein said first latch circuit comprises a first pair of latches, and said second latch circuit comprises a second pair of latches; and wherein each of said first and second pairs of latches comprises edge triggered flip-flops.

6. A system according to claim 1 , wherein said NoC receiver module comprises at least one bisynchronous memory for writing data in synchronization with the transmitter clock signal, and for reading data in synchronization with the receiver clock signal.

7. A system according to claim 6 , wherein said at least one bisynchronous memory comprises a first-in first-out (FIFO) memory; and wherein said FIFO memory is written under control of the first control signal, and is read under control of the second control signal.

8. A system according to claim 1 , wherein said NoC transmitter module comprises a multi-stage buffer for synchronizing at said NoC transmitter module the second control signal to the first control signal.

9. A system according to claim 8 , wherein said multi-stage buffer of said NoC transmitter module comprises:

a third latch circuit for latching and delivering the second control signal in synchronization with a receiver clock signal; and

a fourth latch circuit for latching data provided by said third latch circuit, and delivering the data in synchronization with a transmitter clock signal.

10. A system according to claim 9 , wherein said third and fourth latch circuits are respectively controlled by third and fourth control driving signals that are respectively based on the receiver and transmitter clock signals, with the respective third and fourth control driving signals being in synchronization with the receiver and transmitter clock signals.

11. A system according to claim 9 , wherein said third and fourth latch circuits are configured for alternately latching the second control signal in said third and fourth latch circuits.

12. A system according to claim 10 , wherein said third latch circuit is activated by a rising edge of the third control driving signal, and said fourth latch circuit is activated by a falling edge of the fourth control driving signal.

13. A system according to claim 9 , wherein said third and fourth latch circuits comprise flip-flops.

14. A network-on-chip comprising:

a transmitter module comprising a state machine for generating data;

a receiver module;

a channel between said transmitter module and said receiver module for providing

a first control signal from said transmitter module to said receiver module, and

a second control signal from said receiver module to said transmitter module for initiating data transmission of the data to said receiver module; and

said receiver module comprising a multi-stage buffer, and a controller cooperating therewith for synchronizing the first and second control signals, said multi-stage buffer comprising a first latch circuit for latching and delivering the first control signal in synchronization with a transmitter clock signal and being controlled by a first control driving signal based on the transmitter clock signal, and a second latch circuit for latching data provided by said first latch circuit, and delivering the data in synchronization with a receiver clock signal.

15. A network-on-chip according to claim 14 , wherein said second latch circuit is controlled by a second control driving signal that is based on the receiver clock signal, with the second control driving signal being in synchronization with the receiver clock signal; and wherein said first latch circuit is activated by a rising edge of the first control driving signal, and said second latch circuit is activated by a falling edge of the second control driving signal.

16. A network-on-chip according to claim 14 , wherein said receiver module comprises at least one memory for writing data in synchronization with the transmitter clock signal, and for reading data in synchronization with the receiver clock signal.

17. A method for transmitting data between network-on-chip (NoC) transmitter and receiver modules comprising:

providing a channel between the NoC transmitter module and the NoC receiver module for providing

a first control signal from the NoC transmitter module to the NoC receiver module, and

a second control signal from the NoC receiver module to the NoC transmitter module for initiating data transmission; and

synchronizing the first and second control signals using a multi-stage buffer in at least one of the NoC transmitter and receiver modules, and a controller cooperating therewith for synchronizing the first and second control signals, the multi-stage buffer of the NoC receiver module comprising a first latch circuit for latching and delivering the first control signal in synchronization with a transmitter clock signal and being controlled by a first control driving signal based on the transmitter clock signal, and a second latch circuit for latching data provided by said first latch circuit, and delivering the data in synchronization with a receiver clock signal.

18. A method according to claim 17 , wherein the second latch circuit is controlled by a second control driving signal that is based on the receiver clock signal, with the first and second control driving signals being in synchronization with the transmitter and receiver clock signals, respectively; and wherein the first latch circuit is activated by a rising edge of the first control driving signal, and the second latch circuit is activated by a falling edge of the second control driving signal.

19. A method according to claim 17 , wherein the NoC receiver module comprises at least one memory for writing data in synchronization with the transmitter clock signal, and for reading data in synchronization with the receiver clock signal.