Liquid crystal display having subpixels per color pixel

1. A liquid crystal display comprising:

a substrate;

a gate line disposed on the substrate;

a data line intersecting the gate line;

a thin film transistor comprising a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode;

an interconnection connected to the drain electrode;

a coupling electrode connected to the interconnection;

a passivation layer disposed on the gate line, the data line, the thin film transistor, the interconnection, and the coupling electrode;

a first sub-pixel electrode disposed on the passivation layer and connected to the drain electrode; and

a second sub-pixel electrode disposed on the passivation layer, spaced apart from the first sub-pixel electrode, and overlapping the coupling electrode and the interconnection.

2. The liquid crystal display of claim 1 , wherein the second sub-pixel electrode is approximately trapezoidal and has an edge substantially parallel to the data line.

3. The liquid crystal display of claim 2 , wherein the coupling electrode follows a shape of the second sub-pixel electrode such that the coupling electrode is approximately trapezoidal and has an edge substantially parallel to the data line.

4. The liquid crystal display of claim 2 , wherein the first-subpixel electrode comprises an upper portion disposed above the second sub-pixel electrode in a longitudinal direction, and a lower portion disposed under the second sub-pixel electrode in the longitudinal direction.

5. The liquid crystal display of claim 4 , further comprising:

a storage electrode disposed under the passivation layer and extending along the data line,

wherein the first-subpixel electrode further comprises a longitudinal connection connecting the upper portion and the lower portion of the first sub-pixel electrode,

the first sub-pixel electrode and the second sub-pixel electrode are spaced apart from each other by a gap, and

the gap comprises a longitudinal portion overlapping the storage electrode.

6. The liquid crystal display of claim 2 , wherein a ratio of areas of the first sub-pixel electrode and the second sub-pixel electrode is from about 1:0.85 to about 1:1.15.

7. The liquid crystal display of claim 1 , wherein the interconnection is bent at least once.

8. The liquid crystal display of claim 1 , wherein the passivation layer comprises an inorganic insulating film and an organic insulating film disposed on the inorganic insulating film.

9. The liquid crystal display of claim 1 , further comprising:

a storage electrode line disposed under the passivation layer; and

an overpass disposed on the passivation layer, overlapping the storage electrode line and the gate line, and spaced apart from the first and the second sub-pixel electrodes.

10. A method of manufacturing a thin film transistor array panel, the method comprising:

forming a gate line comprising a gate electrode on a substrate;

forming a gate insulating layer on the gate line;

forming a semiconductor layer on the gate insulating layer;

forming a data line and a drain electrode on the semiconductor layer,

forming a passivation layer on the data line, the drain electrode, and the semiconductor layer, the passivation layer having a contact hole exposing the drain electrode; and

forming a first sub-pixel electrode and a second sub-pixel electrode spaced apart from the first sub-pixel electrode on the passivation layer, the first sub-pixel electrode connected to the drain electrode through the contact hole,

wherein the data line comprises a source electrode, the drain electrode comprising an interconnection and a coupling electrode connected to the interconnection, and the second sub-pixel electrode overlaps the interconnection and the coupling electrode.

11. The method of claim 10 , wherein the second sub-pixel electrode is substantially trapezoidal, and

the coupling electrode is substantially trapezoidal and has an edge substantially parallel to the data line.

12. The method of claim 10 , wherein the interconnection is bent at least once.

13. The method of claim 10 , wherein the formation of the passivation layer comprises:

forming an inorganic insulating film; and

forming an organic insulating film on the inorganic insulating film.

14. The method of claim 10 , further comprising:

forming a storage electrode line under the passivation layer; and

forming an overpass on the passivation layer, the overpass overlapping the storage electrode line and the gate line and spaced apart from the first and the second sub-pixel electrodes.

15. The method of claim 10 , further comprising:

forming a storage electrode under the passivation layer, the storage electrode extending along the data line,

wherein the first-subpixel electrode comprises an upper portion disposed above the second sub-pixel electrode in a longitudinal direction, a lower portion disposed under the second sub-pixel electrode in the longitudinal direction, and a longitudinal connection connecting the upper portion and the lower portion of the first sub-pixel electrode,

the first sub-pixel electrode and the second sub-pixel electrode are spaced apart from each other by a gap, and

the gap comprises a longitudinal portion overlapping the storage electrode.

16. The method of claim 10 , wherein a ratio of areas of the first sub-pixel electrode and the second sub-pixel electrode is from about 1:0.85 to about 1:1.15.