IP Library Granted Patent US 7,754,542
Granted Patent B2
US 7,754,542 · App. 11/960,160 · Granted Jul 13, 2010

Printed TFT array

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,754,542
App. No.
11/960,160
Granted
Jul 13, 2010
Kind
B2
Abstract

An electronic device and/or component is manufactured using additive processing steps, including additive printing steps. A first layer is printed using additive printing techniques wherein a single first material is used to print the first layer in a single processing step. A second layer is printed in more than a single printing step where a first portion of the second layer is printed using a second material and a second portion of the second layer is printed using a third material, and the second and third materials are different from each other.

Claims (21)

1. A method of constructing a thin film transistor array employing additive processing techniques, comprising:

printing a gate layer in a single first printing operation which prints a gate address line and a gate contact with a first material;

depositing a gate dielectric of the gate layer;

printing a source-drain layer in two separate printing operations, including a second printing operation which prints a data address line, a source contact and a drain contact using a second material, and a third printing operation which prints a pixel contact pad using a third material which is different from the first material; and

printing a semiconductor material between the source contact and the drain contact.

2. The method according to claim 1 wherein the second printing operation and the third printing operation result in an overlap between the second material and the third material.

3. The method according to claim 1 wherein the step of printing the gate layer is accomplished by at least one of jet-printing, piezoelectric printing or acoustic printing.

4. The method according to claim 1 wherein the step of depositing the dielectric layer includes spin-coating or slot printing.

5. The method according to claim 1 wherein the step of printing the source-drain layer is accomplished by at least one of jet-printing, piezoelectric printing or acoustic printing.

6. The method according to claim 1 wherein one of the second material and the third material of the source-drain layer is one of silver or and intrinsically conducting material.

7. The method according to claim 1 wherein the silver is part of a nano-particle silver solution.

8. The method according to claim 1 wherein the data address line has a resistance of 1 ohm/sq. or less.

9. The method according to claim 1 wherein the pixel contact pad has a resistance of 1000 ohm/sq. or less.

10. An electronic device created by additive processing techniques, the electronic device comprising:

a first printed layer of the electronic device formed in a single printing operation with a first conductive material, the first printed layer being a gate layer including a gate address line and a gate contact formed with the first conductive material;

a gate dielectric layer formed over the gate layer by a dielectric material;

a second printed layer of the electronic device formed in at least two printing operations, including (i) a first printed portion of the second layer formed with a second conductive material and (ii) a second printed portion of the second layer formed with a third conductive material, different from the second conductive material, the second printed layer being a printed source-drain layer including a data address line, a source contact, and a drain contact formed with a second conductive material, and a pixel contact pad formed with a third conductive material which is different from the second conductive material; and

a semiconductor material between the source contact and the drain contact.

11. The electronic device according to claim 10 wherein the first printed portion of the second printed layer and the second printed portion of the second printed layer overlap.

12. The electronic component according to claim 10 wherein one of the second conductive material or the third conductive material of the second printed layer is one of silver or an intrinsically conductive material.

13. The electronic component according to claim 12 wherein the silver is part of a nano-particle silver solution.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2025
From: XEROX CORPORATION
To: GENESEE VALLEY INNOVATIONS, LLC
Reel/Frame 073842/0479 →
SECOND LIEN NOTES PATENT SECURITY AGREEMENT Recorded Jul 2, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 071785/0550 →
FIRST LIEN NOTES PATENT SECURITY AGREEMENT Recorded Apr 11, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 070824/0001 →
SECURITY INTEREST Recorded Feb 13, 2024
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 066741/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RF 064760/0389 Recorded Feb 13, 2024
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: XEROX CORPORATION
Reel/Frame 068261/0001 →
SECURITY INTEREST Recorded Nov 20, 2023
From: XEROX CORPORATION
To: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 065628/0019 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVAL OF US PATENTS 9356603, 10026651, 10626048 AND INCLUSION OF US PATENT 7167871 PREVIOUSLY RECORDED ON REEL 064038 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 28, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064161/0001 →
SECURITY INTEREST Recorded Jun 22, 2023
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 064760/0389 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064038/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2007
From: STREET, ROBERT A.
To: PALO ALTO RESEARCH CENTER INCORPORATED
Reel/Frame 020272/0476 →