IP Library Granted Patent US 7,755,399
Granted Patent B2
US 7,755,399 · App. 11/960,284 · Granted Jul 13, 2010

High speed comparator circuit with offset cancellation

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Quick Facts
Patent No.
US 7,755,399
App. No.
11/960,284
Granted
Jul 13, 2010
Kind
B2
Abstract

Provided is a comparator circuit that is capable of operating at high speed and canceling an offset voltage with high precision. The comparator circuit includes a second amplifier circuit for amplifying an output of an amplifier circuit and feeding back the amplified output to an input of the amplifier circuit. When the comparator circuit samples the input voltage, the second amplifier circuit conducts feedback and increases a gain to cancel the offset. Also, when the gain of the amplifier circuit is made lower than the gain of the second amplifier circuit, and the comparator circuit compares the input voltage, the comparing operation can be conducted at high speed by separating the amplifier circuit from the feedback of the second amplifier circuit.

Claims (9)

1. A comparator circuit, comprising:

a comparator circuit input terminal;

an input capacitor having one end connected to the comparator circuit input terminal through a first switch and to the ground through a second switch;

an amplifier circuit having a first input terminal connected to another end of the input capacitor and a second input terminal connected to a comparison potential;

a second amplifier circuit having an input terminal connected to an output terminal of the amplifier circuit, and an output terminal connected to the first input terminal of the amplifier circuit through a third switch; and

a latch circuit having an input terminal connected to the output terminal of the amplifier circuit and an output terminal connected to a comparator circuit output terminal,

wherein during a sample operation the third switch is in a connection state and the second amplifier amplifies an output of the amplifier circuit.

2. The comparator circuit according to claim 1 , wherein the third switch is in a disconnection state during a compare and hold operation.

3. The comparator circuit according to claim 1 , wherein a gain of the amplifier circuit is lower than a gain of the second amplifier circuit.

Assignments (4)
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2008
From: UCHIDA, TOSHIYUKI
To: SEIKO INSTRUMENTS, INC.
Reel/Frame 020918/0155 →