Methods of manufacturing semiconductor devices and optical proximity correction
View Patent ↗Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.
1. A method of manufacturing a semiconductor device, the method comprising:
determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device;
adjusting a size of at least one pattern for a feature on a lithography mask by an adjustment amount, wherein the adjustment amount partially compensates for the amount of RIE lag determined; and
patterning the feature in the material layer using the lithography mask.
2. The method according to claim 1 , wherein adjusting the size of the at least one pattern for the feature on the lithography mask by the adjustment amount is a function of the amount of RIE lag determined.
3. The method according to claim 1 , wherein determining the amount of RIE lag comprises calculating the amount of RIE lag.
4. The method according to claim 3 , wherein calculating the amount of RIE lag comprises calculating the amount of RIE considering a type of material of the material layer, a type of etchant of the RIE process, an amount of time of the RIE process, a type of photoresist, and/or the size of the at least one pattern for the feature of the material layer.
5. The method according to claim 1 , wherein determining the amount of RIE lag comprises measuring the amount of RIE lag.
6. The method according to claim 5 , wherein measuring the amount of RIE lag comprises:
providing the lithography mask having a pattern for at least one first feature and a pattern for at least one second feature formed thereon, the pattern for the at least one second feature having a greater width than the pattern for the at least one first feature;
providing the semiconductor device having the material layer disposed thereon;
using the lithography mask to pattern the material layer of the semiconductor device using the RIE process;
measuring a first depth of a portion of the material layer patterned by the pattern for the at least one first feature of the lithography mask;
measuring a second depth of a portion of the material layer patterned by the pattern for the at least one second feature of the lithography mask; and
comparing the second depth with the first depth.
7. The method according to claim 6 , wherein a difference between the second depth and the first depth represents the amount of RIE lag of the RIE process.
8. The method according to claim 1 , further comprising:
fabricating the lithography mask comprising the at least one pattern for the feature of the material layer adjusted by the adjustment amount.
9. A method of manufacturing a semiconductor device, the method comprising:
providing a layout for a material layer of the semiconductor device, the layout comprising a pattern for at least one first feature having a first size and a pattern for at least one second feature having a second size, the second size being greater than the first size;
determining an amount of reactive ion etch (RIE) lag of a RIE process for the material layer of the semiconductor device;
adjusting the layout for the material layer of the semiconductor device to partially compensate for the amount of RIE lag determined;
fabricating a lithography mask comprising the adjusted layout for the material layer; and
using the lithography mask to pattern the semiconductor device.
10. The method according to claim 9 , wherein adjusting the layout for the material layer is a function of the amount of RIE lag determined.
11. The method according to claim 10 , wherein adjusting the layout for the material layer comprises adjusting a width of the pattern for the at least one second feature of the layout in order to reduce a depth within the material layer of features formed by the pattern for the at least one second feature of the layout.
12. The method according to claim 9 , wherein determining the amount of RIE lag comprises calculating the amount of RIE lag.
13. The method according to claim 9 , wherein determining the amount of RIE lag comprises measuring the amount of RIE lag.
14. The method according to claim 13 , wherein measuring the amount of RIE lag comprises:
providing the lithography mask having a pattern for at least one first feature and a pattern for at least one second feature formed thereon, the pattern for the at least one second feature having a greater width than the pattern for the at least one first feature;
providing the semiconductor device having the material layer disposed thereon;
using the lithography mask to pattern the material layer of the semiconductor device using the RIE process;
measuring a first depth of a portion of the material layer patterned by the pattern for the at least one first feature of the lithography mask;
measuring a second depth of a portion of the material layer patterned by the pattern for the at least one second feature of the lithography mask; and
comparing the second depth with the first depth.
15. The method according to claim 14 , wherein a difference between the second depth and the first depth represents the amount of RIE lag of the RIE process.
16. The method according to claim 9 , wherein the method comprises using a modeling tool to determine an amount of adjustment for the RIE lag.
17. The method according to claim 16 , further comprising performing an OPC adjustment on the layout for the material layer using the modeling tool.
18. The method according to claim 9 , wherein determining the amount of adjustment for the RIE lag comprises calculating an area of a cross-section of a pattern formed during the RIE process, and determining a reduced width for the pattern of the at least one second feature.
19. The method according to claim 9 , wherein fabricating the lithography mask comprises adjusting a layout for the lithography mask based on the adjusted layout for the material layer.
20. The method according to claim 19 , wherein adjusting the layout for the lithography mask comprises adjusting the pattern for the at least one second feature in a lateral dimension.
21. The method according to claim 1 , wherein adjusting the size of the at least one pattern for a feature on the lithography mask comprises adjusting the size of the at least one pattern in a lateral dimension.