Adaptive equalization system and method having a lock-up-free quantized feedback DC restoration circuit
View Patent ↗An adaptive equalizer may include one or more equalizing gain stages coupled to an input signal. An automatic gain control circuit may be used to control the gain of the one or more equalizing gain stages, the automatic gain control circuit having an AGC reference input. A dual-output DC restoration circuit may be coupled to the output of the one or more equalizing gain stages for generating a first output signal using a first hysteresis slicer that DC restores the input signal and for generating a second output signal using a second hysteresis slicer that is coupled to the AGC reference input of the automatic gain control circuit, wherein the second hysteresis slicer introducing less hysteresis than the first hysteresis slicer.
1. An adaptive equalizer, comprising:
one or more equalizing gain stages coupled to an input signal to be adaptively equalized;
an automatic gain control circuit for controlling the gain of the one or more equalizing gain stages, the automatic gain control circuit having an AGC reference input; and
a dual-output DC restoration circuit coupled to the output of the one or more equalizing gain stages;
the dual-output DC restoration circuit including a first slicer circuit that generates a first output signal to recover low-frequency components of the input signal, the first slicer circuit being configured to introduce a hysteresis in the first output signal;
the dual-output DC restoration circuit further including a second slicer circuit that generates a second output signal, the second output signal being coupled to the AGC reference input of the automatic gain control circuit, wherein the second slicer circuit is configured to introduce a lesser amount of hysteresis than the hysteresis introduced by the first slicer circuit.
2. The adaptive equalizer of claim 1 , wherein the first slicer circuit is a non-zero hysteresis slicer and the second slicer circuit is a zero hysteresis slicer.
3. The adaptive equalizer of claim 1 , further comprising an output buffer that buffers the first output signal of the dual-output DC restoration circuit.
4. The adaptive equalizer of claim 1 , wherein an output swing of the first output signal of the dual-output DC restoration circuit is tunable independent of the second output signal.
5. The adaptive equalizer of claim 4 , wherein the second output signal is tunable independent of the first output signal to adjust a level of the AGC reference input.
6. The adaptive equalizer of claim 1 , wherein the output of the one or more equalizing gain stages and the first output signal of the dual-output DC restoration circuit are differential signals.
7. The adaptive equalizer of claim 6 , wherein the first slicer circuit includes a differential pair of transistors and a pair of feedback resistors that generate the first output signal.
8. The adaptive equalizer of claim 7 , wherein the first slicer circuit further includes a pair of AC-coupling capacitors that couple the differential output of the one or more equalizing gain stages to the differential pair of transistors and the pair of feedback resistors.
9. The adaptive equalizer of claim 7 , wherein the first slicer circuit further includes a pair of load resistors coupled to the differential pair of transistors, wherein values of the load resistors are selected to set a desired signal swing of the first output signal.
10. The adaptive equalizer of claim 6 , wherein the second output signal of the dual-output DC restoration circuit is also a differential signal.
11. The adaptive equalizer of claim 10 , wherein the second slicer circuit includes a differential pair of transistors that generate the second output signal.
12. The adaptive equalizer of claim 11 , wherein the second slicer circuit further includes a pair of load resistors coupled to the differential pair of transistors, wherein values of the load resistors are selected to set a desired signal level of the second output signal.
13. The adaptive equalizer of claim 10 , wherein the second slicer circuit further includes a tail current source, wherein the tail current source may be adjusted to set a desired signal level of the second output signal.
14. The adaptive equalizer of claim 6 , wherein the first slicer circuit further includes a tail current source, wherein the tail current source may be adjusted to set a desired signal swing of the first output signal.
15. A method for adaptively equalizing an input signal, comprising:
receiving the input signal from a transmission medium;
applying a gain to the input signal to generate an amplified signal, wherein the gain is controlled using an AGC reference input;
generating a quantized output signal using a nonzero hysteresis slicer by introducing a hysteresis and slicing the amplified signal to recover low-frequency components of the input signal; and
generating the AGC reference input using a zero hysteresis slicer by slicing the amplified signal.
16. The method of claim 15 , wherein the gain is controlled by comparing the amplified signal with the AGC reference signal.
17. A method for adaptively equalizing an input signal, comprising:
receiving the input signal from a transmission medium;
applying a gain to the input signal to generate an amplified signal, wherein the gain is controlled using an AGC reference input;
generating a quantized output signal by introducing a hysteresis and slicing the amplified signal to recover low-frequency components of the input signal; and
generating the AGC reference input by slicing the amplified signal;
wherein the quantized output signal is generated using a first hysteresis slicer and the AGC reference signal is generated using a second non-zero hysteresis slicer, wherein the first hysteresis slicer introduces more hysteresis than the second hysteresis slicer.