Load balancing by using clock gears
View Patent ↗An electronic device is capable of monitoring internal components to predict changes in processing power needs. When a prediction is made, a clock control circuit can be instructed to increase the clock signal frequency in response to a predicted increase in processing power needs, or decrease the clock signal frequency in response to a predicted decrease in processing power needs. The control circuit can further balance other clock signal frequencies in order to satisfy constraints such as a power supply constraint.
1. A memory controller in a semiconductor memory device having a plurality of memory cells comprising:
a clock control circuit that receives a master clock signal and generates one or more clock signals;
an error detection and correction code (ECC) circuit that performs error detection and correction processing;
an ECC clock signal, with an ECC clock signal frequency, that is generated by the clock control circuit and sent to the ECC circuit; and
a regulation circuit for predicting a change in the ECC circuit's work load, wherein the ECC clock signal frequency is increased or decreased based on predicted changes in the ECC circuit's work load.
2. The memory controller of claim 1 wherein the regulation circuit for predicting a change in the ECC circuit's work load monitors a number of errors detected by the ECC circuit.
3. A memory controller in a semiconductor memory device having a plurality of memory cells comprising:
a clock control circuit that receives a master clock signal and generates one or more clock signals;
an error detection and correction code (ECC) circuit that performs error detection and correction processing;
an ECC clock signal, with an ECC clock signal frequency, that is generated by the clock control circuit and sent to the ECC circuit;
a regulation circuit for predicting a change in the ECC circuit's work load, wherein the ECC clock signal frequency is increased or decreased based on predicted changes in the ECC circuit's work load; and
a logic circuit that receives a clock signal, with a clock signal frequency, from the clock control circuit where the clock signal frequency is increased or decreased in response to a change in the ECC clock signal frequency, by an amount of that is inversely proportional to the change in the ECC clock signal frequency.
4. A method of balancing power consumption of a memory controller including an error detection and correction code (ECC) circuit that receives an ECC clock signal, comprising:
predicting a processing power need of the ECC circuit needed to process a portion of data;
increasing the ECC clock signal's frequency when the predicted processing power need of the ECC circuit is predicted to increase and decreasing another logic circuit's clock signal frequency; and
decreasing the ECC clock signal's frequency when the predicted processing power need of the ECC circuit is predicted to decrease.
5. The method of claim 4 wherein predicting a processing power need of the ECC circuit includes predicting a processing power need of the ECC circuit to process a portion of data that the memory controller reads from a memory array.
6. The method of claim 5 wherein predicting a processing power need of a ECC circuit comprises:
reading a portion of data from a memory array;
detecting errors from the portion of data; and
predicting a processing power need of the ECC circuit to correct the detected errors from the portion of data.