Method and system for data encryption/decryption key generation and distribution
View Patent ↗System and method for generating and distributing an encryption/decryption key are disclosed and may include generating one or more keys by a key generator integrated within a chip. The generated one or more keys may be communicated directly from the key generator, via an on-chip broadcast serial link, to one of a plurality of on-chip addressable encryption/decryption devices. A particular one of the plurality of on-chip addressable encryption/decryption devices processes one or more received packets that include its own address utilizing the one or more keys. The at least one key may be serialized and encapsulated into a key packet. The encapsulating may include encapsulating an address of the one of the plurality of on-chip addressable encryption/decryption devices in the key packet.
1. A method for generating and distributing an encryption/decryption key, the method comprising:
generating one or more keys by a key generator integrated within a chip;
communicating said generated one or more keys directly from said key generator, via an on-chip broadcast serial link, to one of a plurality of on-chip addressable encryption/decryption devices, wherein a particular one of said plurality of on-chip addressable encryption/decryption devices processes one or more received packets comprising its own address, said processing utilizing said one or more keys received from said key generator integrated within said chip.
2. The method according to claim 1 , comprising serializing said at least one key.
3. The method according to claim 2 , comprising encapsulating said at least one key into a key packet.
4. The method according to claim 3 , wherein said encapsulating comprises encapsulating an address of said one of said plurality of on-chip addressable encryption/decryption devices in said key packet.
5. The method according to claim 4 , wherein said identifying comprises:
receiving said key packet by said one of said plurality of on-chip addressable encryption/decryption devices; and
comparing said address encapsulated within said key packet to said address of said one of said plurality of on-chip addressable encryption/decryption devices.
6. The method according to claim 5 , comprising extracting said at least one key from said key packet, if said comparison results in said encapsulated address within said key packet matching said address of said one of said plurality of on-chip addressable encryption/decryption devices.
7. The method according to claim 6 , comprising utilizing said extracted at least one key by said one of said plurality of on-chip addressable encryption/decryption devices for one of: an encryption and a decryption operation, if said comparison results in said encapsulated address within said key packet matching said address of said one of said plurality of on-chip addressable encryption/decryption devices.
8. The method according to claim 1 , wherein said broadcast serial link is a high-speed serial link to which each of said plurality of on-chip addressable encryption/decryption devices is coupled.
9. A non-transitory machine-readable storage having stored thereon, a computer program having at least one code section for generating and distributing an encryption/ decryption key, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
generating one or more keys by a key generator integrated within a chip;
communicating said generated one or more keys directly from said key generator, via an on-chip broadcast serial link, to one of a plurality of on-chip addressable encryption/decryption devices, wherein a particular one of said plurality of on-chip addressable encryption/decryption devices processes one or more received packets comprising its own address, said processing utilizing said one or more keys received from said key generator integrated within said chip.
10. The non-transitory machine-readable storage according to claim 9 , comprising code for serializing said at least one key.
11. The non-transitory machine-readable storage according to claim 10 , comprising code for encapsulating said at least one key into a key packet.
12. The non-transitory machine-readable storage according to claim 11 , where said code for encapsulating encapsulates an address of said one of said plurality of on-chip addressable encryption/decryption devices in said key packet.
13. The non-transitory machine-readable storage according to claim 12 , wherein said identifying comprises:
code for receiving said key packet by said one of said plurality of on-chip addressable encryption/decryption devices; and
code for comparing said address encapsulated within said key packet to said address of said one of said plurality of on-chip addressable encryption/decryption devices.
14. The non-transitory machine-readable storage according to claim 13 , comprising code for extracting said at least one key from said key packet, if said comparison results in said encapsulated address within said key packet matching said address of said one of said plurality of on-chip addressable encryption/decryption devices.
15. The non-transitory machine-readable storage according to claim 14 , comprising code that utilizes said extracted at least one key for one of: an encryption and a decryption operation, by said one of said plurality of on-chip addressable encryption/decryption devices, if said comparison results in said encapsulated address within said key packet matching said address of said one of said plurality of on-chip addressable encryption/decryption devices.
16. The non-transitory machine-readable storage according to claim 9 , wherein said broadcast serial link is a high-speed serial link to which each of on-chip addressable said plurality of encryption/decryption devices is coupled.
17. A system for generating and distributing an encryption/decryption key, the system comprising:
at least one on-chip key generation module; and
an on-chip broadcast serial link coupled to said on-chip key generation module,
wherein said at least one on-chip key generation module comprises at least one key generator integrated within a chip that enables generation of one or more keys within said chip, said key generator communicates said generated one or more keys directly from said at least one key generator via said on-chip broadcast serial link, to one of a plurality of on-chip addressable encryption/decryption devices, wherein a particular one of said plurality of on-chip addressable encryption/decryption devices processes one or more received packets comprising its own address, said processing utilizing said one or more keys received from said key generator integrated within said chip.
18. The system according to claim 17 , wherein said one of said plurality of on-chip addressable encryption/decryption devices comprises at least one key receiver that enables reception and identification of said transmitted at least one key which is associated with said one of said plurality of on-chip addressable encryption/decryption devices.
19. The system according to claim 18 , wherein said one of said plurality of on-chip addressable encryption/decryption devices comprises at least one encryption/decryption processor that enables processing of said identified at least one key which is associated with one of said encryption/decryption devices.
20. The system according to claim 19 , wherein said at least one key generation module enables serialization of said at least one key.
21. The system according to claim 20 , wherein said at least one key generation module enables encapsulation of said key into a key packet.
22. The system according to claim 21 , wherein said at least one key generation module enables encapsulation of an address of said one of said plurality of on-chip addressable encryption/decryption devices in said key packet.
23. The system according to claim 22 , wherein said at least one key receiver enables receiving of said key packet by said one of a plurality of on-chip addressable encryption/decryption devices and to compare said address encapsulated within said key packet to said address of said one of said plurality of on-chip addressable encryption/decryption devices.
24. The system according to claim 23 , wherein said at least one key receiver enables extraction of said at least one key from said key packet if said comparison results in said encapsulated address within said key packet matching said address of said one of said plurality of on-chip addressable encryption/decryption devices.
25. The system according to claim 24 , wherein said at least one encryption/decryption processor of said one of said plurality of on-chip addressable encryption/decryption devices utilizes said extracted at least one key for one of: an encryption and a decryption operation, if said comparison results in said encapsulated address within said key packet matching said address of said one of said plurality of encryption/decryption devices.
26. The system according to claim 17 , wherein said broadcast serial link is a high-speed serial link.