IP Library Granted Patent US 7,824,949
Granted Patent B2
US 7,824,949 · App. 11/963,008 · Granted Nov 2, 2010

Structure and method for flexible sensor array

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Quick Facts
Patent No.
US 7,824,949
App. No.
11/963,008
Granted
Nov 2, 2010
Kind
B2
Abstract

A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.

Claims (89)

1. A method of forming a sensor array, comprising:

depositing a first semiconductor layer;

depositing a source/drain contact layer over the first semiconductor layer;

depositing a second semiconductor layer on the source/drain contact layer; and

patterning the source/drain contact layer and the second semiconductor layer substantially simultaneously resulting in a patterned second semiconductor layer, a source contact, and a drain contact;

patterning the first semiconductor layer;

forming a protective layer over at least a part of the patterned second semiconductor layer; and

removing the patterned second semiconductor layer exposed by the protective layer;

wherein the patterned second semiconductor layer forms part of a sensor of the sensor array.

2. The method of claim 1 , wherein patterning the first semiconductor layer occurs after forming the protective layer.

3. The method of claim 1 , wherein:

the second semiconductor layer is deposited directly on the source/drain contact layer.

4. The method of claim 1 , further comprising:

depositing an encapsulation layer over the patterned second semiconductor layer.

5. The method of claim 4 , further comprising:

forming an opening in the encapsulation layer to expose the patterned second semiconductor layer.

6. The method of claim 5 , further comprising:

depositing a third semiconductor layer over the second semiconductor layer;

wherein at least part of the second semiconductor layer and at least part of the third semiconductor layer form the sensor.

7. The method of claim 6 , further comprising:

depositing a fourth semiconductor layer over the second semiconductor layer prior to depositing the third semiconductor layer;

wherein the third semiconductor layer is formed over the fourth semiconductor layer.

8. The method of claim 7 , wherein:

the second semiconductor layer is an n-type semiconductor layer;

the third semiconductor layer is a p-type semiconductor layer; and

the fourth semiconductor layer is an intrinsic semiconductor layer.

9. The method of claim 6 , wherein depositing the third semiconductor layer occurs after forming the opening in the encapsulation layer.

10. The method of claim 1 , further comprising:

patterning the first semiconductor layer to form islands after patterning the source/drain contact layer and the second semiconductor layer.

11. The method of claim 10 , further comprising:

depositing a gate conductive layer; and

depositing a gate insulating layer over the gate conductive layer;

wherein the first semiconductor layer is deposited over the gate insulating layer.

12. A method of forming a sensor array, comprising:

depositing a source/drain contact layer;

depositing a first semiconductor layer on the source/drain contact layer; and

patterning the source/drain contact layer and the semiconductor layer substantially simultaneously resulting in a patterned first semiconductor layer;

depositing an encapsulation layer over the patterned first semiconductor layer;

forming an opening in the encapsulation layer to expose the patterned first semiconductor layer; and

depositing a second semiconductor layer in the opening;

wherein at least part of the patterned first semiconductor layer and at least part of the second semiconductor layer form at least part of a sensor of the sensor array;

depositing a third semiconductor layer prior to depositing the source/drain contact layer, the source/drain contact layer deposited over the third semiconductor layer; and

patterning the third semiconductor layer to form an island after patterning the source/drain contact layer and the first semiconductor layer;

wherein depositing the second semiconductor layer includes depositing the second semiconductor layer over the island.

13. The method of claim 12 , wherein forming the opening in the encapsulation layer comprises:

forming the opening in the encapsulation layer such that substantially all of the patterned first semiconductor layer is exposed.

14. A method of forming a sensor array, comprising:

depositing a source/drain contact layer;

depositing a first semiconductor layer on the source/drain contact layer;

patterning the source/drain contact layer and the first semiconductor layer substantially simultaneously resulting in a patterned semiconductor layer;

forming a protective layer over at least a part of the patterned first semiconductor layer;

depositing a second semiconductor layer; and

patterning the second semiconductor layer after forming the protective layer;

wherein:

the source/drain contact layer is deposited over the second semiconductor layer; and

the patterned first semiconductor layer forms part of a sensor of the sensor array.

15. A method of forming a sensor array, comprising:

depositing a source/drain contact layer;

depositing a first semiconductor layer on the source/drain contact layer; and

patterning the source/drain contact layer and the first semiconductor layer substantially simultaneously resulting in a patterned first semiconductor layer;

depositing a second semiconductor layer;

patterning the second semiconductor layer to form islands after patterning the source/drain contact layer and the first semiconductor layer;

wherein:

the source/drain contact layer is deposited over the second semiconductor layer; and

the patterned first semiconductor layer forms part of a sensor of the sensor array.

16. The method of claim 15 , further comprising:

depositing a gate conductive layer; and

depositing a gate insulating layer over the gate conductive layer;

wherein the second semiconductor layer is deposited over the gate insulating layer.

17. A method of forming a sensor array, comprising:

depositing a first semiconductor layer;

depositing a source/drain contact layer over the first semiconductor layer;

depositing a second semiconductor layer on the source/drain contact layer; and

patterning the source/drain contact layer and the second semiconductor layer substantially simultaneously resulting in a patterned second semiconductor layer, a source contact, and a drain contact;

patterning the first semiconductor layer;

depositing an encapsulation layer over the patterned second semiconductor layer; and

forming an opening in the encapsulation layer to expose the patterned second semiconductor layer;

wherein the patterned second semiconductor layer forms part of a sensor of the sensor array.

18. The method of claim 17 , further comprising:

depositing a third semiconductor layer over the second semiconductor layer;

wherein at least part of the second semiconductor layer and at least part of the third semiconductor layer form the sensor.

19. The method of claim 18 , further comprising:

depositing a fourth semiconductor layer over the second semiconductor layer prior to depositing the third semiconductor layer;

wherein the third semiconductor layer is formed over the fourth semiconductor layer.

20. The method of claim 19 , wherein:

the second semiconductor layer is an n-type semiconductor layer;

the third semiconductor layer is a p-type semiconductor layer; and

the fourth semiconductor layer is an intrinsic semiconductor layer.

21. The method of claim 19 , wherein depositing the third semiconductor layer occurs after forming the opening in the encapsulation layer.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2025
From: XEROX CORPORATION
To: GENESEE VALLEY INNOVATIONS, LLC
Reel/Frame 073842/0479 →
SECOND LIEN NOTES PATENT SECURITY AGREEMENT Recorded Jul 2, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 071785/0550 →
FIRST LIEN NOTES PATENT SECURITY AGREEMENT Recorded Apr 11, 2025
From: XEROX CORPORATION
To: U.S. BANK TRUST COMPANY, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 070824/0001 →
SECURITY INTEREST Recorded Feb 13, 2024
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 066741/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RF 064760/0389 Recorded Feb 13, 2024
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: XEROX CORPORATION
Reel/Frame 068261/0001 →
SECURITY INTEREST Recorded Nov 20, 2023
From: XEROX CORPORATION
To: JEFFERIES FINANCE LLC, AS COLLATERAL AGENT
Reel/Frame 065628/0019 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVAL OF US PATENTS 9356603, 10026651, 10626048 AND INCLUSION OF US PATENT 7167871 PREVIOUSLY RECORDED ON REEL 064038 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 28, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064161/0001 →
SECURITY INTEREST Recorded Jun 22, 2023
From: XEROX CORPORATION
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 064760/0389 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2023
From: PALO ALTO RESEARCH CENTER INCORPORATED
To: XEROX CORPORATION
Reel/Frame 064038/0001 →