Memory having read disturb test mode
View Patent ↗Embodiments of the invention relate to the testing and reduction of read disturb failures in a memory, e.g., an array of SRAM cells. A read disturb test mode may be added during wafer sort to identify any marginal memory cells that may fail read disturb, thus minimizing yield loss. The read disturb test mode may include first writing data to the memory. After a predetermined time period, the read disturb test mode reads data from the same memory, and compares the read data with the data previously written to the memory. A repair signal may be generated, when the read data is different from the data previously written to the memory. Additionally, a system may be implemented to reduce read disturb failures in the memory. The system may include a match logic circuit and a data selecting circuit. When a match condition is satisfied, data is read from a register that stores the previous written data, instead of from the memory. The match logic circuit may be selectively enabled or disabled.
1. A system, comprising:
read-disturb reduction logic, including:
a match circuit configured to compare an address associated to a read access with an address associated with a write access, and to generate a match signal responsive to the comparison;
a data selecting circuit configured to select data from two or more data storage locations depending on the match signal; and
read-disturb test mode logic configured to identify read disturb failures during wafer sort.
2. The system of claim 1 , wherein the match circuit includes:
a register to store the address associated with the write access; and
a logic gate to output the match signal when the address associated with the read access matches the address associated with the write access.
3. The system of claim 1 , wherein the data selecting circuit includes:
a register to store data written into a memory element; and
a multiplexer.
4. The system of claim 1 , wherein the read disturb reduction logic is selectively enabled.
5. The system of claim 1 , wherein the match circuit is selectively enabled.
6. The system of claim 3 , wherein the memory element is an array of SRAM cells.
7. The system of claim 1 , wherein the two or more data storage locations comprises at least a register.
8. The system of claim 3 , wherein the match circuit is implemented in a control logic portion of the memory element.
9. The system of claim 3 , wherein the data selecting circuit is implemented in an I/O section of the memory element.
10. A method, comprising:
comparing at a match circuit an address associated to a read access with an address associated with a write access;
generating a match signal responsive to the comparing;
selecting data at a data selecting circuit from two or more data storage locations depending on the match signal; and
identifying read disturb failures during wafer sort using read-disturb test mode logic.
11. The method of claim 10 , wherein the match circuit includes:
a register to store the address associated with the write access; and
a logic gate to output the match signal when the address associated with the read access matches the address associated with the write access.
12. The method of claim 10 , wherein the data selecting circuit includes:
a register to store data written into a memory element; and
a multiplexer.
13. The method of claim 10 , wherein the comparing and generating are selectively enabled.
14. The method of claim 10 , wherein the match circuit is selectively enabled.
15. The method of claim 12 , wherein the memory element is an array of SRAM cells.
16. The method of claim 10 , wherein the two or more data storage locations comprises at least a register.
17. The method of claim 12 , wherein the match circuit is implemented in a control logic portion of the memory element.
18. The method of claim 12 , wherein the data selecting circuit is implemented in an I/O section of the memory element.