Prediction and prevention of uncorrectable memory errors
A method for predicting and preventing uncorrectable errors that may occur while accessing memory in a computer system. The method involves detecting two or more correctable errors from two or more different physical addresses on each of two or more different bit positions from the same DIMM within a specified period of time, with all of the correctable errors occurring within the same checkword. The method also involves detecting two or more correctable errors from two or more different physical addresses on each of three or more different outputs from the same DRAM within a specified period of time, as long as the three outputs do not all correspond to the same relative bit position in their respective checkwords. This allows a computer system which encounters correctable errors to continue to reliably operate without the unnecessary replacement of functioning memory systems.
1. A method for predicting uncorrectable errors in a memory system comprising:
detecting a plurality of correctable errors from a memory device;
analyzing the plurality of correctable errors to identify a pattern of the plurality of correctable errors, the pattern indicative of a future occurrence of an uncorrectable error from the memory device wherein the analyzing operation comprises:
identifying a plurality of first correctable errors from a first bit position of a memory device, the plurality of first correctable errors generated while accessing a first address and a second address in the memory device, wherein the first address and the second addresses are distinct;
identifying a plurality of second correctable errors from a second bit position of the memory device, the plurality of second correctable errors generated while accessing a third address and a fourth address in the memory device, wherein the third address and the fourth addresses are distinct;
identifying a first checkword position associated with the first bit position;
identifying a second checkword position associated with the second bit position; and
identifying whether the first checkword position and the second checkword position occur in a same checkword construct comprising a plurality of checkword positions populated by a plurality of bit positions of the memory device; and
determining that the plurality of first correctable errors occurs at the first bit position and the plurality of second correctable errors occurs at the second bit position; and
providing an indicator of the future occurrence of the uncorrectable error from the memory device.
2. The method of claim 1 , wherein the analyzing operation identifies a plurality of locations in the memory device of the plurality of correctable errors and determines whether the plurality of correctable errors are indicative of future correctable errors at the plurality of locations in the memory device.
3. The method of claim 1 , wherein the analyzing operation further comprises:
identifying whether the plurality of first correctable errors and the plurality of second correctable errors occur within a specified period of time.
4. The method of claim 3 wherein the specified period of time is 72 hours.
5. A method for predicting uncorrectable errors in a memory system comprising:
detecting a plurality of correctable errors from a memory device;
analyzing the plurality of correctable errors to identify a pattern of the plurality of correctable errors, the pattern indicative of a future occurrence of an uncorrectable error from the memory device wherein the analyzing operation comprises:
identifying a plurality of first correctable errors from a first output pin of the memory device, the plurality of first correctable errors generated while accessing a first address and a second address in the memory device, wherein the first address and the second address are distinct;
identifying a plurality of second correctable errors from a second output pin of the memory device, the plurality of second correctable errors generated while accessing a third address and a fourth address in the memory device, wherein the third address and the fourth address are distinct; and
identifying a plurality of third correctable errors from a third output pin of the memory device, the plurality of third correctable errors generated while accessing a fifth address and a sixth address in the memory device, wherein the fifth address and the sixth address are distinct;
identifying a first checkword associated with the first output pin, the first output pin corresponding to a bit position in the first checkword;
identifying a second checkword associated with the second output pin, the second output pin corresponding to a bit position in the second checkword;
identifying a third checkword associated with the third output pin, the third output pin corresponding to a bit position in the third checkword;
identifying whether the corresponding bit positions of the first output pin, the second output pin, and the third output pin in the first checkword, the second checkword and the third checkword, respectively, are the same; and
providing an indicator of the future occurrence of the uncorrectable error from the memory device.
6. The method of claim 5 , wherein the analyzing operation further comprises:
identifying whether the first correctable errors, the second correctable errors, and the third correctable errors occur within a specified period of time.
7. The method of claim 6 wherein the specified period of time is 72 hours.
8. The method of claim 1 , wherein the providing operation further comprises:
generating a message to a user warning of the future occurrence of the uncorrectable error.
9. The method of claim 8 , wherein the message instructs the user to replace the memory device.
10. The method of claim 1 wherein the memory device is a DIMM.
11. The method of claim 1 wherein the memory device is a DRAM.
12. A computing system for predicting uncorrectable errors in memory comprising:
a memory controller in communication with at least one memory device, the memory controller configured to perform error detection of data stored in the at least one memory device; and
a processor in communication with the memory controller and the at least one memory device, the processor configured to:
detect a plurality of first correctable errors from a first bit position of a memory device, the plurality of first correctable errors detected while accessing a first address and a second address in the memory device, wherein the first address and the second address are distinct;
detect a plurality of second correctable errors from a second bit position of the memory device, the plurality of second correctable errors detected while accessing a third address and a fourth address in the memory device, wherein the third address and the fourth address are distinct;
determine that the plurality of first correctable errors occurs at the first bit position and the plurality of second correctable errors occurs at the second bit position;
identify a first checkword position associated with the first bit position;
identify a second checkword position associated with the second bit position;
determine that the first checkword position and the second checkword position are in a same checkword construct comprising a plurality of checkword positions populated by a plurality of bit positions of the memory device; and
identify the memory device as having a high probability of an uncorrectable error.
13. The system of claim 12 , wherein the processor is further configured to:
determine that the first correctable errors and the second correctable errors occur within a specified period of time.
14. The system of claim 13 wherein the specified period of time is 72 hours.
15. The system of claim 12 , wherein the processor is further configured to:
generate a message to a user warning of a future occurrence of an uncorrectable error.
16. The system of claim 15 , wherein the message instructs the user to replace the memory device.
17. The system of claim 12 wherein the memory device is a DIMM.