Frequency multiplier

1. A frequency multiplier comprising:

a switching component having a plurality of differential pairs of transistors; and

a gain stage wherein a common mode feedback generated by the switching component is provided to the gain stage, the common mode feedback is combined with an input signal to the switching component to generate a frequency multiplied output signal, wherein the frequency is multiplied by three times.

2. A frequency multiplier in accordance with claim 1 wherein the common mode feedback comprises even harmonics.

3. A frequency multiplier in accordance with claim 2 wherein the even harmonics comprise at least a 2 nd harmonic.

4. A frequency multiplier in accordance with claim 1 wherein the gain stage comprises a transistor and a source of each transistor in one of a pair of the differential pairs of transistors is connected to a drain of the transistor of the gain stage.

5. A frequency multiplier in accordance with claim 1 wherein a drain of one of each of the differential pairs of transistors is connected to a drain of one of each of the transistors in a different differential pair of the transistors.

6. A frequency multiplier in accordance with claim 1 wherein the gain stage is connected to an output of the switching component and is configured to amplify the common mode feedback.

7. A frequency multiplier in accordance with claim 1 wherein each of the transistors in the differential pairs of transistors is switched on and off during different portions of a cycle of an input signal.

8. A frequency multiplier in accordance with claim 1 further comprising an additional transistor connected to one of the differential pairs of transistors, the additional transistor being DC biased.

9. A frequency multiplier in accordance with claim 1 wherein opposite phases of an input signal are applied to different ones of the transistors in each of the differential pairs of transistors.

10. A frequency multiplier in accordance with claim 1 further comprising a first load connected to one of each of the transistors in the differential pairs of transistors and a second load connect to the other transistor in the differential pairs of transistors.

11. A frequency multiplier comprising:

a switching component having a plurality of differential pairs of transistors; and

a gain stage wherein a common mode feedback generated by the switching component is provided to the gain stage, and wherein a single input signal is provided to the switching component and the switching component is configured to generate a frequency multiplied signal having a frequency that is triple the single input signal.

12. An apparatus comprising:

a signal generator configured to generate an input signal; and

a frequency multiplier configured to generate a frequency multiplied output signal from a single input signal of the signal generator and having a frequency that is one of three times and five times a frequency of the single input signal, wherein the frequency multiplied output signal is generated using the single input signal and a common-mode feedback signal generated by the frequency multiplier.

13. An apparatus in accordance with claim 12 wherein the frequency multiplier is configured in a balanced topology to compensate for fundamental components generated and the frequency multiplier has no bandpass filter.

14. An apparatus in accordance with claim 12 wherein the frequency multiplied output is a tripled differential signal.

15. An apparatus comprising:

a signal generator configured to generate an input signal; and

a frequency multiplier configured to generate a frequency multiplied output signal from a single input signal of the signal generator and having a frequency that is one of three times and five times a frequency of the single input signal, wherein the frequency multiplier comprises a gain stage configured to amplify a common-mode feedback signal to generate the frequency multiplied output signal.

16. An apparatus comprising:

a signal generator configured to generate an input signal; and

a frequency multiplier configured to generate a frequency multiplied output signal from a single input signal of the signal generator and having a frequency that is one of three times and five times a frequency of the single input signal, wherein the frequency multiplier comprises a plurality of differential pairs of transistors providing switching operation to generate in phase harmonics based on the single input signal, the in phase harmonics defining a common-mode feedback used to generate the frequency multiplied output.

17. A method for generating a multiplied frequency signal, the method comprising:

switching pairs of differential transistors with a single input signal;

generating harmonics based on the switching;

generating a common-mode feedback based on even harmonics from the generated harmonics;

amplifying the common-mode feedback harmonics with a gain stage to generate an amplified common-mode signal; and

using the amplified common-mode signal combined with the single input signal to generate a multiplied frequency output signal, wherein the multiplied frequency output signal is a signal having triple the frequency of the single input signal.