IP Library Granted Patent US 8,014,969
Granted Patent B2
US 8,014,969 · App. 11/964,719 · Granted Sep 6, 2011

Test apparatus, test method and manufacturing method

Assignee: Advantest Corporation
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Quick Facts
Patent No.
US 8,014,969
App. No.
11/964,719
Granted
Sep 6, 2011
Kind
B2
Abstract

There is provided a test apparatus for testing a plurality of devices under test. The test apparatus includes a signal input section that applies a test signal to the devices under test so as to cause the devices under test to concurrently output response signals, a combining section that generates a single combination signal by using the response signals output from the devices under test, and a judging section that judges whether the devices under test operate normally with reference to the combination signal.

Claims (35)

1. A test apparatus for testing a plurality of devices under test, comprising:

a signal input section that applies a test signal to the devices under test so as to cause the devices under test to concurrently output response signals that are the same as each other;

a combining section that generates a single combination signal by using the response signals output from the devices under test;

a judging section that judges whether the devices under test operate normally with reference to the combination signal; and

a calibration section that measures, prior to the test of the devices under test, a level of the combination signal which is generated when causing one or more of the devices under test and the one or more remaining devices under test to output response signals such that the response signals output by the one or more devices under test have logic values different from those output by the one or more remaining devices under test, and designates the threshold value in accordance with the measured level of the combination signal, wherein

the combining section generates a signal by combining the response signals in an analog manner, as the combination signal, and

the judging section judges whether the devices under test operate normally by determining whether a signal level of the combination signal is higher than a predetermined threshold value at a predetermined timing.

2. The test apparatus as set forth in claim 1 , further comprising

a level comparing section that compares the signal level of the combination signal with the threshold value, wherein

the combining section includes therein a plurality of wires provided in a one-to-one correspondence with the devices under test, and

each of the wires electrically connects a signal output terminal of a corresponding one of the devices under test to a signal input terminal of the level comparing section, so that the wires generate the combination signal and apply the generated combination signal to the level comparing section.

3. The test apparatus as set forth in claim 1 , wherein

prior to the test, the calibration section sequentially varies the number of the devices under test that output the response signals having the different logic value from the remaining devices under test, measures levels of the combination signal in a one-to-one correspondence with the sequentially varied numbers, and calculates threshold values with reference to the measured levels of the combination signal, and

the judging section detects how many of the devices under test operate normally, with reference to a level comparison result signal obtained by comparing the level of the combination signal generated by combining the response signals during the test of the devices under test with each of the calculated threshold values.

4. The test apparatus as set forth in claim 1 , wherein

when judging that one or more of the devices under test do not operate normally, the judging section individually judges whether the devices under test operate normally with reference to the individual response signals.

5. The test apparatus as set forth in claim 4 , further comprising

an enabling control section that supplies a signal to one or more of the devices under test which are judged by the judging section not to operate normally, the signal indicating that the one or more devices under test are prohibited from outputting the response signals, and permits the test apparatus to continue testing the remaining devices under test.

6. The test apparatus as set forth in claim 1 , wherein

prior to the test of the devices under test, the judging section confirms that an output of each of the devices under test is not fixed to high impedance, with reference to the combination signal generated by combining the response signals.

7. The test apparatus as set forth in claim 1 , wherein

the judging section judges whether all of the devices under test operate normally or at least one of the devices under test operates abnormally, with reference to the combination signal.

8. A test method for testing a plurality of devices under test, comprising:

applying a test signal to the devices under test so as to cause the devices under test to concurrently output response signals that are the same as each other;

generating a single combination signal using the response signals output from the devices under test by combining the response signals in an analog manner, as the combination signal;

judging whether the devices under test operate normally with reference to the combination signal by determining whether a signal level of the combination signal is higher than a predetermined threshold value at a predetermined timing; and

measuring, prior to the test of the devices under test, a level of the combination signal which is generated when causing one or more of the devices under test and the one or more remaining devices under test to output response signals such that the response signals output by the one or more devices under test have logic values different from those output by the one or more remaining devices under test, and designating the threshold value in accordance with the measured level of the combination signal.

9. A manufacturing method for manufacturing electronic devices, comprising:

forming a plurality of electronic devices; and

selecting one or more of the electronic devices which operate normally by testing the formed electronic devices, to manufacture normally-operating electronic devices, wherein

the selecting includes:

applying a test signal to the electronic devices so as to cause the electronic devices to concurrently output response signals that are the same as each other;

generating a single combination signal using the response signals output from the electronic devices by combining the response signals in an analog manner, as the combination signal; and

judging whether the electronic devices operate normally with reference to the combination signal by determining whether a signal level of the combination signal is higher than a predetermined threshold value at a predetermined timing,

the manufacturing method further including measuring, prior to the selecting, a level of the combination signal which is generated when causing one or more of the electronic devices and the one or more remaining electronic devices to output response signals such that the response signals output by the one or more electronic devices have logic values different from those output by the one or more remaining electronic devices, and designating the threshold value in accordance with the measured level of the combination signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2008
From: NIIJIMA, HIROKATSU; HARA, KOJI; KOZUKA, NORIYOSHI; SHIBATA, KOHEI; SAKANIWA, TETSUYA
To: ADVANTEST CORPORATION
Reel/Frame 020605/0546 →
Continuity (3)
Continuation PCTJP2007066136 · Aug 20, 2007
Provisional Application 60849710 · Oct 5, 2006
Related Publication 20090240365A1 · Sep 24, 2009