Balanced Grey code utilization to increase NVM endurance

1. A counting device, comprising:

a memory comprising a set of memory cells, comprising multiple groups of the memory cells that are configured to store respective count words of a count code, the count words comprising at least a less significant word and a more significant word; and

a controller, which is coupled to the memory cells so as to make a first assignment of the groups of the memory cells that are to store the respective count words, which includes assigning first and second groups of the memory cells to store the less significant word and the more significant word, respectively, and to increment, in response to occurrences of a count input, the less significant word from an initial value up to a first limit in each of a plurality of successive first iterations, and to increment, in response to reaching the first limit in each of the successive first iterations, the more significant word from an initial value up to a second limit in each of a plurality of successive second iterations, and upon reaching the second limit, to make a second assignment, different from the first assignment, of the groups of the memory cells that are to store the less significant word and the more significant word, respectively, and to continue the first and second iterations subject to the second assignment.

2. The device according to claim 1 , wherein each of the count words comprises a respective balanced count code.

3. The device according to claim 2 , wherein the balanced count code is a balanced Gray code.

4. The device according to claim 1 , wherein the memory is a non-volatile memory.

5. The device according to claim 4 , wherein the non-volatile memory comprises a Flash memory.

6. The device according to claim 1 , wherein the limit for each iteration is defined by a maximum value given by a number of the bits in each of the count words.

7. The device according to claim 1 , wherein at least one of the memory cells is assigned to store a state indicator, and wherein the controller is coupled to increment the state indicator upon making the second assignment.

8. The device according to claim 7 , wherein the controller is configured to read a value of the count code by decoding the state indicator so as to identify the groups of the memory cells storing the less significant word and the more significant word.

9. The device according to claim 1 , wherein the less significant word and the more significant word are swapped between the first and second groups of the memory cells upon making the second assignment.

10. The device according to claim 1 , wherein the count code comprises, in addition to the less significant and more significant words, at least a third count word, which is stored in a third group of the memory cells in accordance with the first assignment, and wherein the less significant word, the more significant word, and the third count word are swapped among the groups of the memory cells upon making the second assignment.

11. The device according to claim 10 , wherein the third count word has a level of significance that is intermediate between the more and less significant words.

12. A method for counting, comprising:

defining a count code comprising multiple count words, which comprise at least a less significant word and a more significant word;

making a first assignment of first and second groups of memory cells, among multiple groups of the memory cells in a memory, to store the less significant word and the more significant word, respectively;

in response to occurrences of a count input, incrementing the less significant word from an initial value up to a first limit in each of a plurality of successive first iterations;

in response to reaching the first limit in each of the successive first iterations, incrementing the more significant word from an initial value up to a second limit in each of a plurality of successive second iterations;

in response to reaching the second limit, making a second assignment, different from the first assignment, of the groups of the memory cells that are to store the less significant and the more significant word; and

continuing the first and second iterations subject to the second assignment.

13. The method according to claim 12 , wherein each of the count words comprises a respective balanced count code.

14. The method according to claim 13 , wherein the balanced count code is a balanced Gray code.

15. The method according to claim 12 , wherein the memory is a non-volatile memory.

16. The method according to claim 15 , wherein the non-volatile memory comprises a Flash memory.

17. The method according to claim 12 , wherein the limit for each iteration is defined by the maximum value of the memory word.

18. The method according to claim 12 , wherein the method comprises assigning at least one of the memory cells to store a state indicator, and upon making the second assignment, incrementing the state indicator.

19. The method according to claim 18 , wherein the method comprises decoding the state indicator so as to identify the groups of the memory cells storing the less significant word and the more significant word in order to read a value of the count code.

20. The method according to claim 12 , wherein making the second assignment comprises swapping the less significant word and the more significant word between the first and second groups of the memory cells.

21. The method according to claim 12 , wherein the count code comprises at least a third count word in addition to the less significant and more significant words, and wherein making the first assignment comprises assigning a third group of the memory cells to store the third count word, and wherein making the second assignment comprises swapping the less significant word, the more significant word, and the third count word among the groups of the memory cells.

22. The method according to claim 21 , wherein the third count word has a level of significance that is intermediate between the more and less significant words.