MMPP analysis of network traffic using a transition window
View Patent ↗Data communication in network traffic is modeled in real time and is analyzed using a 2-state Markov modified Poissen process (MMPP). The traffic inter-arrival times for bursty and idle states define a transition window [λ 1 max , λ 2 min ] represented by the boundary values λ 1 max for the inter-arrival time for bursty traffic, and λ 2 min for the inter-arrival time for idle traffic. Changes in the values of λ 1 max and λ 2 min are tracked over time, and the size of the transition window is enlarged or decreased based upon relative changes in these values. If the inter-rival times for the bursty state and the idle state become approximately equal, the model defaults to a single state model. The modeling is applicable to the synchronization of polling and blocking in a low-latency network system. This permits the adoptive selection of poll or block to maximize CPU utilization and interrupt latency.
1. A computer-implemented system, comprising:
a processor; and
a network interface in communication with the processor;
wherein the processor is configured to minimize latency in data communication in network traffic based upon an inter-arrival time of individual data packets at the network interface by:
a) applying a 2-state Markov modulated Poisson process (MMPP) algorithm useful for determining whether the packet arrival rates are ‘bursty’ (λ 1 ) representing heavy traffic conditions or ‘idle’ (λ 2 ) representing light traffic conditions to network traffic at the network interface;
b) wherein a transition window [λ 1 max , λ 2 min ] is represented by boundary values λ 1 max for the inter-arrival time for bursty traffic, and λ 2 min for the inter-arrival time for idle traffic,
c) wherein the processor is configured to determine a probability ρ 1 that a packet inter-arrival time is occurring in bursty traffic or a probability ρ 2 that the arrival time is occurring in idle traffic, and
d) wherein the processor is configured to, based upon said probability ρ 1 or ρ 2 determination, either block or poll a transfer of data packets.
2. The system according to claim 1 , wherein the processor is further configured to carrying out a modeling and analysis of network traffic in real-time.
3. The system according to claim 1 wherein the processor is configured to assign a mean value of λ 1 mean to a bursty packet inter-arrival time and to assign a mean value of λ 2 mean to an idle packet inter-arrival time and wherein λ 2 mean <<λ 1 mean .
4. The system according to claim 3 , wherein the processor is configured to default to a single state MMPP model as λ 2 mean approximates λ 1 mean .
5. The system according to claim 1 , wherein the processor is further configured to track changes in the values of λ 1 max and λ 2 min over time and to enlarge or decrease the size of the transition window based upon relative changes in the values.
6. The system according to claim 5 , wherein the processor is configured to track the changes by computing a mean inter-arrival time of a plurality of packets.
7. The system according to claim 1 , wherein the processor is configured to synchronize a user process with a completion of a receive operation at the network interface, and to determine a burst length during the bursty state by an interrupt latency time.