Digital radio frequency switch matrix

1. A digital radio frequency switch matrix, adapted to receive a plurality of inputs, generate a plurality of outputs, and simultaneously route a plurality of inputs to any of a plurality of outputs, comprising:

an array comprising a plurality of inputs, having a plurality of associated clocks;

a digital control input adapted to receive a signal indicative of a mapping between at least one of said inputs and at least one respective output;

a digital logic array, responsive to said digital control input for simultaneously communicating a plurality of signals each corresponding to one of the plurality of inputs and a respective associated clock to at least one of said outputs indicated by the digital control input; and

an array of the outputs, each adapted to present a regenerated signal corresponding to one of the plurality of inputs and a respective associated synchronized regenerated clock maintaining accurate relative timing therebetween.

2. The digital radio frequency switch matrix according to claim 1 , wherein said digital control input is adapted to receive said signal indicative of a mapping between an input and a respective output as a serialized digital sequence.

3. The digital radio frequency switch matrix according to claim 1 , wherein said digital radio frequency switch matrix is adapted to simultaneously multicast a signal represented in a single input to a plurality of outputs.

4. The digital radio frequency switch matrix according to claim 1 , wherein said input is routed through a set-reset flip-flop cell and said associated clock is routed through a non-destructive readout cell.

5. The digital radio frequency switch matrix according to claim 1 , wherein said digital radio frequency switch matrix is configured as a Banyan network.

6. The digital radio frequency switch matrix according to claim 1 , wherein said digital radio frequency switch matrix is configured as an N×M crosspoint switch matrix.

7. The digital radio frequency switch matrix according to claim 6 , further comprising a delay compensation network to ensure equal delays between different pairs of respective input and respective output.

8. The digital radio frequency switch matrix according to claim 7 , wherein the delay compensation is selectively tunable to achieve different delay characteristics.

9. The digital radio frequency switch matrix according to claim 1 , wherein a mapping of input to output by the digital logic array is dynamically reconfigurable.

10. The digital radio frequency switch matrix according to claim 1 , wherein at least one associated clock has a rate of 40 Gbps.

11. The digital radio frequency switch matrix according to claim 1 , wherein the digital logic array comprises a plurality of Josephson Junctions.

12. The digital radio frequency switch matrix according to claim 1 , wherein the digital logic array comprises superconducting devices.

13. The digital radio frequency switch matrix according to claim 1 , wherein at least one input receives a digital data stream from an analog-to-digital converter.

14. The digital radio frequency switch matrix according to claim 1 , wherein at least one output presents a digital data stream to a digital-to-analog converter.

15. The digital radio frequency switch matrix according to claim 1 , wherein at least one input receives a digital data stream from a digital channelizing converter, based on a plurality of data streams assigned different channels within the data stream.

16. The digital radio frequency switch matrix according to claim 1 , wherein at least one output presents a digital data stream to a digital channelizing receiver, producing a plurality of data streams assigned different channels within the data stream.

17. A digital radio frequency switching method, comprising:

receiving a plurality of inputs, having a plurality of associated clocks;

receiving a signal indicative of a mapping between at least one of said inputs and at least one respective output from a digital control input;

simultaneously communicating a plurality of signals, each corresponding to one of the plurality of inputs and a respective associated clock to at least one of said outputs indicated by the digital control input through a digital logic array; and

presenting as an output a regenerated signal corresponding to one of the plurality of inputs and a respective associated synchronized regenerated clock, maintaining accurate relative timing therebetween.

18. The method according to claim 17 , wherein said signal comprises a serialized digital sequence.

19. The method according to claim 17 , an input signal is simultaneously multicast to a plurality of outputs.

20. The method according to claim 17 , further comprising the step of ensuring equal delays though a plurality of signal paths between different pairs of respective input and respective output.

21. The method according to claim 17 , further comprising the step of selectively tuning a delay within a signal path achieve different delay characteristics.

22. The method according to claim 17 , further comprising the step of dynamically configuring a mapping of input to output by the digital logic array.

23. The method according to claim 17 , wherein at least one input receives a digital data stream from an analog-to-digital converter or at least one output presents a digital data stream to a digital-to-analog converter.

24. The method according to claim 17 , wherein at least one input receives a digital data stream from a digital channelizing converter, based on a plurality of data streams assigned different channels within the data stream or at least one output presents a digital data stream to a digital channelizing receiver, producing a plurality of data streams assigned different channels within the data stream.