SiGe device with SiGe-embedded dummy pattern for alleviating micro-loading effect
View Patent ↗A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe.
1. A semiconductor device with dummy patterns for alleviating micro-loading effect, comprising:
a semiconductor substrate having thereon a middle annular region between an inner region and an outer region;
a SiGe device on the semiconductor substrate within the inner region;
a plurality of first dummy patterns provided on the semiconductor substrate within the middle annular region, wherein at least one of the first dummy patterns contains SiGe; and
a plurality of second dummy patterns provided on the semiconductor within the outer region, wherein the second dummy patterns do not contain SiGe.
2. A semiconductor device with dummy patterns for alleviating micro-loading effect, comprising:
a semiconductor substrate having thereon a middle annular region between an inner region and an outer region;
a SiGe device on the semiconductor substrate within the inner region; and
a plurality of first dummy patterns provided on the semiconductor substrate within the middle annular region, wherein at least one of the first dummy patterns contains SiGe;
wherein the plurality of first dummy patterns comprise dummy poly silicon patterns and SiGe-embedded dummy diffusion regions, and wherein the dummy poly silicon patterns and the SiGe-embedded dummy diffusion regions are arranged in an alternate manner within the middle annular region.
3. The semiconductor device with dummy patterns for alleviating micro-loading effect according to claim 2 , wherein the dummy poly silicon pattern does not overlap with the SiGe-embedded dummy diffusion region.
4. A semiconductor device with dummy patterns for alleviating micro-loading effect, comprising:
a semiconductor substrate having thereon a middle annular region between an inner region and an outer region;
a SiGe device on the semiconductor substrate within the inner region; and
a plurality of first dummy patterns provided on the semiconductor substrate within the middle annular region, wherein at least one of the first dummy patterns contains SiGe;
wherein the SiGe device is a P-channel metal-oxide-semiconductor (PMOS) transistor.
5. A semiconductor device with dummy patterns for alleviating micro-loading effect, comprising:
a semiconductor substrate having thereon a middle annular region between an inner region and an outer region;
a SiGe device on the semiconductor substrate within the inner region; and
a plurality of first dummy patterns provided on the semiconductor substrate within the middle annular region, wherein at least one of the first dummy patterns contains SiGe;
wherein the SiGe device functions as a circuit component of mixed-signal circuits, RF circuits or analog circuits.
6. A semiconductor device, comprising:
a semiconductor substrate having thereon a middle annular region between an inner region and an outer region;
a SiGe device on the semiconductor substrate within the inner region;
a plurality of SiGe-embedded, cell-like dummy patterns provided on the semiconductor substrate within the middle annular region, wherein each of the SiGe-embedded, cell-like dummy patterns has substantially the same structure as that of the SiGe device; and
a plurality of SiGe-free, cell-like dummy patterns in the outer region.
7. The semiconductor device according to claim 6 , wherein the SiGe device is electrically isolated by shallow trench isolation (STI).
8. The semiconductor device according to claim 6 , wherein the SiGe device is a P-channel metal-oxide-semiconductor (PMOS) transistor.
9. The semiconductor device according to claim 8 , wherein the SiGe device comprises a gate stack, a P+ source diffusion region, a P+ drain diffusion region, and a P channel between the P+ source diffusion region and the P+ drain diffusion region.
10. The semiconductor device according to claim 9 , wherein a SiGe stressor layer is formed on the P+ source diffusion region and the P+ drain diffusion region.
11. The semiconductor device according to claim 6 , wherein each of the SiGe-embedded, cell-like dummy pattern comprises a dummy gate, a dummy P+ diffusion region and a dummy P+ diffusion region, and wherein a SiGe layer is formed on the dummy P+ diffusion region and the dummy P+ diffusion region.
12. The semiconductor device according to claim 6 , wherein the SiGe device functions as a circuit component of mixed-signal circuits, RF circuits or analog circuits.
13. The semiconductor device according to claim 6 , wherein the semiconductor substrate comprises a silicon substrate.