High precision continuous time gmC BPF tuning
View Patent ↗High precision continuous time g m C BPF (Band Pass Filter) tuning. A novel approach is presented by which a continuous time signal serves as a BPF control voltage for tuning of a BPF within a communication device (e.g., transceiver or receiver). A PLL (Phase Locked Loop) tunes the center frequency of the BPF using this continuous time signal, and the PLL oscillates at the center frequency of the BPF. The BPF is implemented as a g m C (transconductance-capacitance) filter, and the PLL is implemented using a number of g m (transconductance) cells as well. The PLL's g m cells and the BPF's g m cells are substantially identical in form. All of these g m cells are operated within their respective linear regions. This similarity of g m cells within the PLL and the BPF provide for substantial immunity to environmental perturbations including temperature and humidity changes as well as fluctuations of power supply voltages.
1. A PLL (Phase Locked Loop) implemented to perform continuous time BPF (Band Pass Filter) tuning, the PLL comprising:
a PFD (Phase/Frequency Detector) implemented to determine a phase difference between transitions of a feedback signal and an input signal;
a CP (Charge Pump) implemented to convert the phase difference into a charge pump current;
a loop filter implemented to process the charge pump current thereby generating a VCO (Voltage Controlled Oscillator) control voltage and a BPF (Band Pass Filter) control voltage;
a VCO (Voltage Controlled Oscillator) implemented to process the VCO control voltage thereby generating a recovered clock, wherein the feedback signal is derived from the recovered clock and the VCO includes a plurality of g m (transconductance) cells; and wherein:
when processing the charge pump current thereby generating the BPF control voltage, the loop filter for ensuring that any spur content or glitch content within the charge pump current is filtered from the BPF control voltage; and
the BPF control voltage for determining a tuning frequency of a BPF to which the PLL is communicatively coupled.
2. The PLL of claim 1 , wherein:
the loop filter is implemented as a LPF (Low Pass Filter).
3. The PLL of claim 1 , further comprising:
an amplitude detector implemented to detect an amplitude of the recovered clock and to bias the plurality of g m cells of the VCO such that each g m cell of the plurality of g m cells operating within its linear operating region.
4. The PLL of claim 1 , further comprising:
a voltage buffer implemented to process the recovered clock generating the feedback signal.
5. The PLL of claim 1 , wherein:
the plurality of g m cells included within the VCO is a first plurality of g m cells;
the BPF is implemented as a g m C (transconductance-capacitance) filter that includes a second plurality of g m cells; and
the first plurality of g m cells and the second plurality of g m cells of the g m C filter include similar g m cells.
6. The PLL of claim 5 , wherein:
the tuning frequency of the BPF is a center frequency of the BPF; and
the BPF control voltage for biasing the second plurality of g m cells such that each g m cell of the second plurality of g m cells operating within its linear operating region.
7. The PLL of claim 5 , wherein:
the similarity of the g m cells of the first plurality of g m cells and the second plurality of g m cells providing immunity to environmental perturbation of the PLL and the BPF.
8. The PLL of claim 7 , wherein:
the environmental perturbation of the PLL and the BPF is at least one of a temperature change, a humidity change, and a change in a power supply voltage.
9. The PLL of claim 1 , wherein:
the BPF control voltage is a continuous time analog voltage signal.
10. The PLL of claim 1 , wherein:
the PLL is implemented within an AFE (Analog Front End) of a communication device; and
the communication device is a transceiver or a receiver.
11. A PLL (Phase Locked Loop) implemented to perform continuous time BPF (Band Pass Filter) tuning, the PLL comprising:
a PFD (Phase/Frequency Detector) implemented to determine a phase difference between transitions of a feedback signal and an input signal;
a CP (Charge Pump) implemented to convert the phase difference into a charge pump current;
a loop filter implemented to process the charge pump current thereby generating a VCO (Voltage Controlled Oscillator) control voltage and a BPF (Band Pass Filter) control voltage, wherein the loop filter is implemented as a LPF (Low Pass Filter);
a VCO (Voltage Controlled Oscillator) implemented to process the VCO control voltage thereby generating a recovered clock, wherein the feedback signal is derived from the recovered clock and the VCO includes a first plurality of g m (transconductance) cells; and wherein:
when processing the charge pump current thereby generating the BPF control voltage, the loop filter for ensuring that any spur content or glitch content within the charge pump current is filtered from the BPF control voltage;
the BPF control voltage for determining a tuning frequency of a BPF to which the PLL is communicatively coupled;
the BPF is implemented as a g m C (transconductance-capacitance) filter that includes a second plurality of g m cells;
the first plurality of g m cells and the second plurality of g m cells of the g m C filter include similar g m cells; and
each g m cell of the first plurality of g m cells and the second plurality of g m cells operating within its linear operating region.
12. The PLL of claim 11 , further comprising:
an amplitude detector implemented to detect an amplitude of the recovered clock and to bias the first plurality of g m cells of the VCO such that each g m cell of the first plurality of g m cells operating within its linear operating region; and
a voltage buffer implemented to process the recovered clock generating the feedback signal.
13. The PLL of claim 11 , wherein:
the similarity of the g m cells of the first plurality of g m cells and the second plurality of g m cells providing immunity to environmental perturbation of the PLL and the BPF.
14. The PLL of claim 13 , wherein:
the environmental perturbation of the PLL and the BPF is at least one of a temperature change, a humidity change, and a change in a power supply voltage.
15. The PLL of claim 11 , wherein:
the PLL is implemented within an AFE (Analog Front End) of a communication device; and
the communication device is a transceiver or a receiver.
16. A PLL (Phase Locked Loop) implemented to perform continuous time BPF (Band Pass Filter) tuning, the PLL comprising:
a PFD (Phase/Frequency Detector) implemented to determine a phase difference between transitions of a feedback signal and an input signal;
a CP (Charge Pump) implemented to convert the phase difference into a charge pump current;
a loop filter implemented to process the charge pump current thereby generating a VCO (Voltage Controlled Oscillator) control voltage and a BPF (Band Pass Filter) control voltage;
a VCO (Voltage Controlled Oscillator) implemented to process the VCO control voltage thereby generating a recovered clock, wherein the feedback signal is derived from the recovered clock and the VCO includes a first plurality of g m (transconductance) cells;
an amplitude detector implemented to detect an amplitude of the recovered clock and to bias the first plurality of g m cells of the VCO such that each g m cell of the first plurality of g m cells operating within its linear operating region; and
a voltage buffer implemented to process the recovered clock generating the feedback signal; and wherein:
when processing the charge pump current thereby generating the BPF control voltage, the loop filter for ensuring that any spur content or glitch content within the charge pump current is filtered from the BPF control voltage;
the BPF control voltage for determining a tuning frequency of a BPF to which the PLL is communicatively coupled; and
the BPF is implemented as a g m C (transconductance-capacitance) filter that includes a second plurality of g m cells.
17. The PLL of claim 16 , wherein:
the first plurality of g m cells and the second plurality of g m cells of the g m C filter include similar g m cells;
each g m cell of the second plurality of g m cells operating within its linear operating region; and
the similarity of the g m cells of the first plurality of g m cells and the second plurality of g m cells providing immunity to environmental perturbation of the PLL and the BPF.
18. The PLL of claim 16 , wherein:
the loop filter is implemented as a LPF (Low Pass Filter).
19. The PLL of claim 16 , wherein:
the tuning frequency of the BPF is a center frequency of the BPF; and
the BPF control voltage biases for biasing the second plurality of g m cells such that each g m cell of the second plurality of g m cells operating within its linear operating region.
20. The PLL of claim 16 , wherein:
the PLL is implemented within an AFE (Analog Front End) of a communication device; and
the communication device is a transceiver or a receiver.