Method and apparatus for serial communication using clock-embedded signals
View Patent ↗Apparatus for serial communication using embedded clock signals includes a data divider for dividing a data stream into odd-numbered and even-numbered data streams; a clock-embedded signal generator for generating odd-numbered and even-numbered embedded clock signals by pulse amplitude modulating the odd-numbered and even-numbered data streams and, when an external clock is input, inverting polarities of the pulse amplitude modulated odd-numbered and even-numbered data streams; a clock-embedded signal recovery unit for recovering the odd-numbered and even-numbered data streams by comparing amplitudes of the odd-numbered and even-numbered embedded clock signals with reference voltages, respectively, and recovering synchronization information of the clock by detecting when amplitude polarities of the odd-numbered and even-numbered embedded clock signals are inverted; and a data integrator for integrating the odd-numbered and even-numbered data streams and supplying the result as the data stream.
1. An apparatus for serial communication using embedded clock signals, comprising:
a data divider for dividing a data stream into odd-numbered and even-numbered data streams;
a clock-embedded signal generator for generating odd-numbered and even-numbered embedded clock signals by pulse amplitude modulating the odd-numbered and even-numbered data streams and, when an external clock is input, inverting polarities of the pulse amplitude modulated odd-numbered and even-numbered data streams;
a clock-embedded signal recovery unit for recovering the odd-numbered and even-numbered data streams by comparing amplitudes of the odd-numbered and even-numbered embedded clock signals with reference voltages, respectively, and recovering synchronization information of the clock by detecting when amplitude polarities of the odd-numbered and even-numbered embedded clock signals are inverted; and
a data integrator for integrating the odd-numbered and even-numbered data streams and supplying the result as the data stream.
2. The apparatus of claim 1 , wherein the clock-embedded signal generator comprises:
a first signal generator for generating the odd-numbered embedded clock signal; and
a second signal generator for generating the even-numbered embedded clock signal,
wherein the first and second signal generators pulse amplitude modulate the odd-numbered and even-numbered data streams to have amplitudes having different polarities, respectively.
3. The apparatus of claim 2 , wherein the first signal generator comprises:
a first positive polarity signal generator for pulse amplitude modulating the odd-numbered data stream into a signal having two positive polarity amplitudes;
a first negative polarity signal generator for pulse amplitude modulating the odd-numbered data stream into a signal having two negative polarity amplitudes; and
a first clock information inserter for alternately switching the odd-numbered data stream to the positive polarity signal generator and the negative polarity signal generator in response to the clock.
4. The apparatus of claim 3 , wherein the second signal generator comprises:
a second positive polarity signal generator for pulse amplitude modulating the even-numbered data stream into a signal having two positive polarity amplitudes;
a second negative polarity signal generator for pulse amplitude modulating the even-numbered data stream into a signal having two negative polarity amplitudes; and
a second clock information inserter for alternately switching the even-numbered data stream to the negative polarity signal generator and the positive polarity signal generator in response to the clock.
5. A method for serial communication using embedded clock signals, the method comprising:
dividing a data stream into odd-numbered and even-numbered data streams;
pulse amplitude modulating the odd-numbered and even-numbered data streams into reference level voltages, respectively;
generating odd-numbered and even-numbered embedded clock signals by inverting polarities of amplitudes corresponding to the odd-numbered and even-numbered data streams in response to a clock;
recovering the odd-numbered and even-numbered data streams by comparing amplitudes of the odd-numbered and even-numbered embedded clock signals with reference voltages, respectively; and
recovering synchronization information of the clock by detecting when polarities of amplitudes of the odd-numbered and even-numbered embedded clock signals are inverted.
6. The method of claim 5 , wherein the reference level voltages comprises a first level voltage of positive polarity, a second level voltage of positive polarity, a first level voltage of negative polarity, and a second level voltage of negative polarity.
7. The method of claim 6 , wherein the odd-numbered and even-numbered data streams are modulated by varying polarities.
8. The method of claim 7 , wherein the odd-numbered and even-numbered data streams are converted into a first level voltage of positive polarity or a first level voltage of negative polarity when a data value of the odd-numbered and even-numbered data streams is “1”, and converted into a second level voltage of positive polarity or a second level voltage of negative polarity when the data value of the odd-numbered and even-numbered data streams is “0”.
9. The method of claim 6 , wherein, the reference voltages comprise a first reference voltage having an intermediate value between the first level voltage of positive polarity and the second level voltage of positive polarity, and a second reference voltage having an intermediate value between the first level voltage of negative polarity and the second level voltage of negative polarity.
10. The method of claim 9 , wherein the odd-numbered and even-numbered data streams are recovered by comparing amplitude voltages of the odd-numbered and even-numbered embedded clock signals with the reference voltages.