Low power frequency division and local oscillator generation
View Patent ↗A plurality of inverters are arranged serially to form a ring oscillator and coupled to receive a reference clock signal. The reference clock signal is used to switch the inverters on and off so that not all of the inverters are on at a same time. The ring oscillator circuit is used as a divider circuit to divide the frequency of the reference clock signal to produce a local oscillator signal at a second frequency.
1. An apparatus comprising:
a phase-locked loop (PLL) coupled to receive a reference input and to generate a reference PLL signal at its output at a first frequency; and
a frequency divider circuit coupled to receive the reference PLL signal and to divide the first frequency to generate a local oscillator signal at a second frequency, the frequency divider circuit including a series of inverters that are switched on and off by the reference PLL signal.
2. The apparatus of claim 1 , wherein the series of inverters are differential latched inverters.
3. The apparatus of claim 1 , further including a buffer coupled between the PLL and the frequency divider circuit to buffer the reference PLL signal.
4. The apparatus of claim 1 , wherein the inverters are gated tri-state inverters.
5. The apparatus of claim 2 , wherein the frequency divider circuit generates both an in-phase local oscillator signal and a quadrature local oscillator signal.
6. An apparatus comprising:
a buffer to receive a phase-locked loop (PLL) signal from a PLL at a first frequency and to output a differential buffered PLL signal; and
a frequency divider circuit coupled to receive the differential buffered PLL signal and to divide the first frequency to generate a local oscillator signal at a second frequency, the frequency divider circuit including a plurality of inverters that are arranged serially to form a ring oscillator, in which the differential buffered PLL signal is used to switch the inverters on and off so that not all of the inverters are on at a same time to reduce power consumption.
7. The apparatus of claim 6 , wherein the inverters are differential latched inverters.
8. The apparatus of claim 6 , wherein the inverters are gated tri-state inverters.
9. The apparatus of claim 6 , wherein the ring oscillator generates both an in-phase local oscillator signal and a quadrature local oscillator signal.
10. The apparatus of claim 6 further comprising a mixing module coupled to receive the local oscillator signal for radio frequency (RF) signal conversion, in which the buffer, frequency divider, mixer and a PLL are part of a RF front end and constructed on a same integrated circuit.
11. A method comprising:
generating a reference clock signal at an output of a phase-locked loop (PLL) at a first clock frequency;
using the reference clock signal to switch on and off a plurality of inverters that are arranged serially to form a ring oscillator, in which time-switching of the inverters causes not all of the inverters to be turned on at a same time to substantially reduce power consumption; and
generating a local oscillator signal as an output from the ring oscillator in which the output from the ring oscillator is at a second frequency that is approximately the first frequency divided by a factor of N.
12. The method of claim 11 , further including buffering the reference clock signal to generate a differential buffered clock signal that is coupled to the inverters.
13. The method claim 12 , wherein generating the local oscillator signal includes generating both an in-phase local oscillator signal and a quadrature local oscillator signal.