Thin film transistor and flat panel display device
A thin film transistor, a method of fabricating the same, and a flat panel display device including the same, are provided. According to the method, low resistance regions and high resistance regions can be manufactured through one doping process. The thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate and including source and drain regions, high resistance regions smaller than the source and drain regions, a channel region, and connection regions disposed between the high resistance regions and the channel region; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer above the channel region; an interlayer insulating layer disposed on the gate electrode; and source and drain electrodes disposed on the interlayer insulating layer and electrically connected to the source and drain regions, respectively.
1. A thin film transistor comprising:
a substrate;
a semiconductor layer on the substrate and comprising source and drain regions, high resistance regions having a smaller width and a longer length than the source and drain regions, a channel region, and connection regions between respective said high resistance regions and the channel region;
a gate insulating layer on the semiconductor layer;
a gate electrode on the gate insulating layer above the channel region;
an interlayer insulating layer on the gate electrode; and
source and drain electrodes on the interlayer insulating layer and electrically connected to the source and drain regions, respectively,
wherein one of the high resistance regions is between the channel region and the source region, and another one of the high resistance regions is between the channel region and the drain region, and
wherein the length of each of the high resistance regions is taken along a path of the high resistance region between the respective connection region and the respective source or drain region.
2. The thin film transistor according to claim 1 , wherein the high resistance regions have a length that is 1.3-10 times larger than that of the source and drain regions.
3. The thin film transistor according to claim 2 , wherein the high resistance regions have a length of 3-20 μm.
4. The thin film transistor according to claim 1 , wherein the high resistance regions have a width that is 25-100% of a width of the source and drain regions.
5. The thin film transistor according to claim 4 , wherein the width of the high resistance regions is 1-4 μm.
6. The thin film transistor according to claim 1 , wherein the high resistance regions have a rectangular shape or a zigzag shape.
7. The thin film transistor according to claim 1 , wherein the connection regions have an area that is 5-50% of an area of the channel region.
8. The thin film transistor according to claim 1 , wherein the connection regions have at least one tapered angle.
9. The thin film transistor according to claim 1 , wherein the connection regions have at least one curved surface.
10. A flat panel display device comprising:
a substrate;
a semiconductor layer on the substrate and comprising source and drain regions, high resistance regions having a smaller width and a longer length than the source and drain regions, a channel region, and connection regions between respective said high resistance regions and the channel region;
a gate insulating layer on the semiconductor layer;
a gate electrode on the gate insulating layer above the channel region;
an interlayer insulating layer on the gate electrode;
source and drain electrodes on the interlayer insulating layer and electrically connected to the source and drain regions, respectively; and
a display element coupled with the source electrode or the drain electrode, wherein the display element is adapted to display an image in accordance with voltages applied at the gate electrode and the source and drain electrodes,
wherein one of the high resistance regions is between the channel region and the source region, and another one of the high resistance regions is between the channel region and the drain region, and
wherein the length of each of the high resistance regions is taken along a path of the high resistance region between the respective connection region and the respective source or drain region.
11. The flat panel display device according to claim 10 , wherein the high resistance regions have a length of 1.3-10 times larger than that of the source and drain regions.
12. The flat panel display device according to claim 11 , wherein the high resistance regions have a length of 3-20 μm.
13. The flat panel display device according to claim 10 , wherein the high resistance regions have a width that is 25-100% of a width of the source and drain regions.
14. The flat panel display device according to claim 13 , wherein the width of the high resistance regions is 1-4 μm.
15. The flat panel display device according to claim 10 , wherein the high resistance regions have a rectangular shape or a zigzag shape.
16. The flat panel display device according to claim 10 , wherein the connection regions have an area that is 5-50% of an area the channel region.
17. The flat panel display device according to claim 10 , wherein the connection regions have at least one tapered angle.
18. The flat panel display device according to claim 10 , wherein the connection regions have at least one curved surface.
19. A thin film transistor comprising:
a substrate;
a semiconductor layer on the substrate and comprising source and drain regions, high resistance regions having a smaller width or a longer length than the source and drain regions, a channel region, and connection regions between respective said high resistance regions and the channel region;
a gate insulating layer on the semiconductor layer;
a gate electrode on the gate insulating layer above the channel region;
an interlayer insulating layer on the gate electrode; and
source and drain electrodes on the interlayer insulating layer and electrically connected to the source and drain regions, respectively,
wherein one of the high resistance regions is between the channel region and the source region, and another one of the high resistance regions is between the channel region and the drain region,
wherein the length of each of the high resistance regions is taken along a path of the high resistance region between the respective connection region and the respective source or drain region,
wherein the high resistance regions and the source and drain regions have substantially a same dopant concentration, and
wherein the width and length of the high resistance regions are chosen with respect to those of the source and drain regions so that the high resistance regions have higher resistance than that of the source and drain regions.