Differential signaling system and flat panel display with the same
View Patent ↗A differential signaling system and a flat panel display using the same. The differential signaling system includes a first wiring and a second wiring connected to a sending end and a receiving end as a differential signal line; a termination resistor connected between the first wiring and the second wiring in the receiving end side; and a programmable compensation circuit connected to the termination resistor in parallel. The programmable compensation circuits includes n switches to receive each bit of an input digital control signal; first resistors connected between a source electrode of each of the switches and the first wiring; and second resistors connected between a drain electrode of each of the switches and the second wiring.
1. A differential signaling system comprising:
a plurality of pairs of first wirings and a second wirings connected to sending ends and receiving ends as differential signal lines; and
a plurality of display data driving circuits connected to the plurality of pairs of first wirings and second wirings, each plurality of display data driving circuits including a programmable compensation circuit connected to a termination resistor in parallel installed between the first and second wirings, the plurality of programmable compensation circuits including a plurality of switches configured to receive an input digital control signal, first n resistors connected between a source electrode of each of the switches and the first wiring, and second n resistors connected between a drain electrode of each of the switches and the second wiring, each bit of the input digital control signal being configured to vary the impedance of the programmable compensation circuit,
wherein an impedance of each of the display data driving circuits is adjusted by the corresponding programmable compensation circuit based on the impedance of a corresponding pair of first wiring and second wiring.
2. The differential signaling system according to claim 1 , wherein the number of the switches is the number of digital bits of a control signal for controlling the programmable compensation circuit.
3. The differential signaling system according to claim 1 , wherein the switch is a transistor having a predetermined minimum distributed gate voltage.
4. The differential signaling system according to claim 1 , wherein resistances of the first n resistors and the second n resistors have the same value.
5. The differential signaling system according to claim 4 , wherein the resistance of the first resistors and the resistance of the second resistors is (N/M)R b , where R b represents a resistance value of a resistor included in the programmable compensation circuit, N is a digital control signal bit number inputted to the programmable compensation circuit, and M is a logic high bit number of an input digital control signal.
6. The differential signaling system according to claim 4 , wherein M is equal to 8 and N is equal to 2.
7. A differential signaling system comprising:
a display panel having a plurality of data wirings and gate wirings arranged to intersect each other;
a controller to receive an image signal, to generate a control signal, and to output the image signal through first and second wirings as a differential signal line;
a gate driver to receive the control signal from the controller and to apply a scan signal to the gate wirings; and
a plurality of display data driving circuits, each including a programmable compensation circuit connected to a terminal resistor in parallel installed between the first and second wirings, the programmable compensation circuits configured to automatically control an impedance value of the corresponding display data driving circuit based on a differential impedance value of the corresponding differential signal line, each of the display data driving circuits including a data driver to receive the image signal and/or the control signal from the controller through the first and second wirings and to apply the image signal to the data wirings;
wherein the programmable compensation circuits each include a plurality of switches to receive each bit of an input digital control signal, each bit of the input digital control signal being configured to vary the impedance of the programmable compensation circuit, first n resistors connected between a source electrode of each of the switches and the first wiring; and second n resistors connected between a drain electrode of each of the switches and the second wiring.
8. The differential signaling system according to claim 7 , wherein the number of the switches is the number of digital bits of a control signal for controlling the programmable compensation circuit.
9. The differential signaling system according to claim 7 , wherein the switches are transistors having a predetermined minimum distributed gate voltage.
10. The differential signaling system as claimed in claim 7 , wherein resistances of the first n resistors and the second n resistors have the same value.
11. The differential signaling system as claimed in claim 10 , wherein the resistance of the first resistors and the resistance of the second resistors is (N/M)R b , wherein R b represents a resistance value of a resistor included in the programmable compensation circuit, N is a digital control signal bit number inputted to the programmable compensation circuit, and M is a logic high bit number of an input digital control signal.
12. The differential signaling system as claimed in claim 10 , wherein M is equal to 8 and N is equal to 2.
13. A flat panel display comprising:
a display panel having data wirings and gate wirings arranged so as to intersect;
a controller to receive an input signal, to generate a control signal, and to output the control signal and the input signal to the display panel so as to display an image;
a gate driver to receive the control signal from the controller and to apply a scan signal to the gate wirings; and
a plurality of display data driving circuits connected in parallel and configured to receive the image signal and/or the control signal from the controller via first and second wirings and to apply the image signal to the data wirings;
wherein each of the plurality of display data driving circuits includes a programmable compensation circuit to dynamically adjust an impedance of the display data driving circuit so as to match a differential impedance of the controller, wherein each of the programmable compensation circuits comprises a plurality of switches to receive each bit of the control signal, each bit of the input digital control signal being configured to vary the impedance of the programmable compensation circuit,
wherein an impedance of each of the display data driving circuits is adjusted by the corresponding programmable compensation circuit based on the impedance of a corresponding pair of first wiring and second wiring.
14. The flat panel display according to claim 13 , wherein each of the programmable compensation circuits comprises:
a plurality of first resistors connected between a source electrode of each of the plurality of switches and the first wiring; and
a plurality of second resistors connected between a drain electrode of each of the switches and the second wiring.
15. The flat panel display according to claim 14 , wherein each switch is a transistor having a predetermined minimum distributed gate voltage.
16. The flat panel display according to claim 14 , wherein the number of switches is a number of bits of a control signal to control the programmable compensation circuit.
17. The flat panel display according to claim 14 , wherein a resistance of the first resistors is the same as a resistance of the second resistors.
18. The flat panel display according to claim 17 , wherein the resistance of the first resistors and the resistance of the second resistors is (N/M)R b , wherein R b represents a resistance value of a resistor included in the programmable compensation circuit, N is a number of bits of the control signal to control the programmable compensation circuit, and M is a logic high bit number of the control signal to control the programmable compensation circuit.
19. The flat panel display according to claim 18 , wherein M is 8 and N is 2.
20. The flat panel display according to claim 13 , wherein the display data driving circuits each comprise a termination resistor connecting the first and second wirings.
21. The flat panel display according to claim 13 , wherein the programmable compensation circuit compensates for variations in the differential impedance of the controller.