Solid-state imaging device and camera system
View Patent ↗When making a potential of a floating node 0V at the time of nonselection, electrons leak from the floating node to a photodiode and noise is generated. A MOS type solid-state imaging device comprised of unit pixels 10 , each having a photodiode 11 , a transfer transistor 12 for transferring a signal of this photodiode 11 to a floating node N 11 , an amplifier transistor 13 for outputting a signal of the floating node N 11 to a vertical signal line 22 , and a reset transistor 14 for resetting the floating node N 11 , arranged in a matrix, wherein, as a buffer final stage 29 for driving a drain line 23 , a buffer final stage having an inverter configuration formed by arranging a P-type MOS transistor on a ground side is used, thereby making the potential of the floating node N 11 for example 0.5V at the time of nonselection and preventing electrons from leaking to the photodiode 11 through the transfer transistor 12.
1. A solid-state imaging device, comprising:
a photoelectric conversion element;
a transfer transistor of a first conductivity type for transferring a signal of said photoelectric conversion element to a floating node;
an amplifier transistor for outputting a signal of said floating node to a signal line;
a reset transistor of the first conductivity type for resetting said floating node; and
a driving means for driving an interconnect to which an electrode of said reset transistor on an opposite side to said floating node is connected, wherein said driving means has:
a first transistor of a second conductivity type connected between said interconnect and a voltage source and a second transistor of the second conductivity type connected between said interconnect and a ground and driven by a signal having an inverse polarity to that for said first transistor and further wherein the driving means selectively applies a voltage level substantially equal to a channel voltage of the second transistor during a reset operation which is greater than 0V.
2. A solid-state imaging device as set forth in claim 1 , wherein the channel voltage when said second transistor is on is from 0.4V to 0.7V.
3. A solid-state imaging device as set forth in claim 1 , wherein said first transistor and said second transistor differ in on/off timings.
4. A solid-state imaging device as set forth in claim 1 , wherein said amplifier transistor has one main electrode electrically connected to a main electrode of said reset transistor at the opposite side of said floating node.
5. A solid-state imaging device as set forth in claim 4 , further comprising a means for cutting the supply of the current to said signal line before an on/off operation of said first transistor and second transistor.
6. A camera system, comprising:
a solid-state imaging device,
an optical system for guiding incident light to an imaging portion of said solid-state imaging device, and
a signal processing circuit for processing an output signal of said solid-state imaging device, wherein said solid-state imaging device has:
a photoelectric conversion element,
a transfer transistor of a first conductivity type for transferring a signal of said photoelectric conversion element to a floating node,
an amplifier transistor for outputting a signal of said floating node to a signal line,
a reset transistor of the first conductivity type for resetting said floating node,
a first transistor of a second conductivity type connected between the interconnect to which the main electrode of said reset transistor on the opposite side to said floating node is connected and the voltage source, and
a second transistor of the second conductivity type connected between said interconnect and the ground and driven by a signal having an inverse polarity to that for said first transistor and further wherein a voltage level substantially equal to a channel voltage of the second transistor is applied to the reset transistor during a reset operation which is greater than 0V.
7. A camera system as set forth in claim 6 , wherein a channel voltage of said second transistor is from 0.4V to 0.7V.
8. A camera system as set forth in claim 6 , wherein said first transistor and said second transistor differ in on/off timings.
9. A camera system as set forth in claim 6 , wherein said amplifier transistor has one main electrode electrically connected to a main electrode of said reset transistor at the opposite side of said floating node.
10. A camera system as set forth in claim 9 , further comprising a means for cutting the supply of the current to said signal line before an on/off operation of said first transistor and second transistor.