Granted Patent B2

US 7,812,655 · App. 11/973,884 · Granted Oct 12, 2010

Abstract

Claims (68)

1. A device, comprising:

a delay-locked loop circuitry configured to trigger generation of first-type edges of a target signal for use with a digital pulse-width modulator in a digital feedback loop of a switched-mode power supply, and

a main control circuitry configured to control operation of said delay-locked loop circuitry in a way that said delay-locked loop circuitry is turned on before generation of each first-type edge of said target signal and turned off after generation of each said first-type edge, wherein said delay-locked loop circuitry is configured to trigger generation of said first-type edges of said target signal at least partially based on a first clock signal, wherein said delay-locked loop circuitry comprises:

a delay-locked loop configured to output a plurality of delayed representations of said first clock signal, and

a combination circuitry configured to combine said plurality of delayed representations of said first clock signal into a signal via which said delay-locked loop circuitry triggers generation of said first-type edges of said target signal, wherein an operation of said combination circuitry is controlled by said main control circuitry, wherein said delay-locked loop comprises:

a switch configured to receive a representation of said first clock signal;

a line of delay elements connected to an output of said switch, wherein said delay elements in said line of delay elements generate said plurality of delayed representations of said first clock signal;

a phase detector configured to control said delay elements based on a comparison of two different representations of said first clock signal, and

a switch and phase detector control circuitry configured to control operation of said switch of said delay-locked loop and to turn on and off said phase detector of said delay-locked loop in response to at least one control signal generated by said main control circuitry.

2. The device of claim 1 , wherein said main control circuitry is further configured to trigger generation of second-type edges of said target signal.

3. The device of claim 1 , wherein said main control circuitry controls operation of said delay-locked loop circuitry at least partially based on an input signal received by said main control circuitry.

4. The device of claim 1 , further comprising a switching circuitry configured to generate said target signal, wherein generation of said first-type edges of said target signal is triggered via a switching signal generated by said delay-locked loop circuitry.

5. The device of claim 1 , further comprising:

a clock multiplier configured to change a frequency of a second clock signal to obtain said first clock signal.

6. The device of claim 5 , wherein said clock multiplier comprises a delay-locked loop.

7. The device of claim 6 , wherein said delay-locked loop comprises:

a line of delay elements that is fed with said second clock signal,

a phase detector configured to control said delay elements based on a comparison of said second clock signal and a delayed representation of said second clock signal,

at least one combination circuitry configured to combine delayed representations of said second clock signal to obtain a switching signal, and

a switching circuitry configured to generate said first clock signal at least partially based on said switching signal of said at least one combination circuitry.

8. The device of claim 1 , wherein said switch and phase detector control circuitry is configured to close said switch of said delay-locked loop before said phase detector of said delay-locked loop is turned on, if said at least one control signal indicates that said delay-locked loop circuitry shall be turned on to generate a first-type edge of said target signal.

9. The device of claim 1 , wherein said switch and phase detector control circuitry is configured to open said switch of said delay-locked loop and to turn off said phase detector of said delay-locked loop, if said at least one control signal indicates that said delay-locked loop circuitry shall be turned off after generation of a first-type edge.

10. The device of claim 1 , wherein said phase detector controls operation of said delay elements via a control voltage, and wherein said phase detector comprises a capacitor for storing a specific control voltage during the time period said phase detector is turned off.

11. The device of claim 1 , wherein said target signal is a pulse-width modulated signal.

12. The device of claim 11 , wherein said pulse-width modulated signal controls a switching circuitry of a switched-mode power supply.

13. The device of claim 1 , further comprising:

a switching circuitry configured to apply a supply voltage to a load via an inductive element in response to said target signal; and

an analog-to-digital converter configured to convert an analog voltage signal tapped between said inductive element and said load into a digital signal, wherein said main control circuitry controls operation of said delay-locked loop circuitry at least partially based on said digital signal.

14. A device, comprising:

means for triggering generation of first-type edges of a target signal for use with a digital pulse-width modulator in a digital feedback loop of a switched-mode power supply, and

means for controlling operation of said means for triggering generation of said first-type edges of said target signal in a way that said means for triggering generation of said first-type edges of said target signal is turned on before generation of each first-type edge of said target signal and turned off after generation of each said first-type edge, wherein said means for triggering is configured to trigger generation of said first-type edges of said target signal at least partially based on a first clock signal, wherein said means for triggering comprises:

means for outputting a plurality of delayed representations of said first clock signal, and

means for combining said plurality of delayed representations of said first clock signal into a signal via which said means for triggering triggers generation of said first-type edges of said target signal, wherein an operation of said means for combining is controlled by said means for controlling, wherein said means for outputting a plurality of delayed representations comprises:

means for receiving a representation of said first clock signal;

a line of delay elements connected to an output of said means for receiving a representation of said first clock signal, wherein said delay elements in said line of delay elements generate said plurality of delayed representations of said first clock signal;

means for controlling said delay elements based on a comparison of two different representations of said first clock signal,

means for controlling operation of said means for receiving a representation of said first clock signal and for turning on and off said means for controlling said delay elements in response to at least one control signal generated by said means for controlling operation of said means for triggering generation of said first-type edges.

15. The device of claim 14 , wherein said target signal is a pulse-width modulated signal, and wherein said device further comprises:

means for controlling a switching circuitry of a switched-mode power supply at least partially based on said pulse-width modulated signal.

16. A chip, implementing:

a delay-locked loop circuitry configured to trigger generation of first-type edges of a target signal, and

a main control circuitry configured to control operation of said delay-locked loop circuitry in a way that said delay-locked loop circuitry is turned on before generation of each first-type edge of said target signal and turned off after generation of each said first-type edge, wherein said delay-locked loop circuitry is configured to trigger generation of said first-type edges of said target signal at least partially based on a first clock signal, wherein said delay-locked loop circuitry comprises:

a delay-locked loop configured to output a plurality of delayed representations of said first clock signal, and

a combination circuitry configured to combine said plurality of delayed representations of said first clock signal into a signal via which said delay-locked loop circuitry triggers generation of said first-type edges of said target signal, wherein an operation of said combination circuitry is controlled by said main control circuitry, wherein said delay-locked loop comprises:

a switch configured to receive a representation of said first clock signal;

a line of delay elements connected to an output of said switch, wherein said delay elements in said line of delay elements generate said plurality of delayed representations of said first clock signal;

a phase detector configured to control said delay elements based on a comparison of two different representations of said first clock signal, and

a switch and phase detector control circuitry configured to control operation of said switch of said delay-locked loop and to turn on and off said phase detector of said delay-locked loop in response to at least one control signal generated by said main control circuitry.

17. The chip of claim 16 , wherein said target signal is a pulse-width modulated signal that controls a switching circuitry of a switched-mode power supply.

18. A method, comprising:

controlling operation of a delay-locked loop circuitry, wherein said delay-locked loop circuitry is configured to trigger generation of first-type edges of a target signal for use with a digital pulse-width modulator in a digital feedback loop of a switched-mode power supply, and wherein operation of the delay-locked loop circuitry is controlled in a way that said delay-locked loop circuitry is turned on before generation of each first-type edge of said target signal and turned off after generation of each said first-type edge, triggering generation of said first-type edges of said target signal at least partially based on a first clock signal,

outputting a plurality of delayed representations of said first clock signal,

combining said plurality of delayed representations of said first clock signal into a signal used for triggering generation of said first-type edges of said target signal,

receiving a representation of said first clock signal;

controlling delay elements used to generate said plurality of delayed representations of said first clock signal based on a comparison of two different representations of said first clock signal, and

controlling said receiving and turning on and off said controlling of said delay elements in response to at least one control signal.

19. The method of claim 18 , wherein said target signal is a pulse-width modulated signal, and wherein said method further comprises:

controlling a switching circuitry of a switched-mode power supply at least partially based on said pulse-width modulated signal.

20. A computer-readable medium having a computer program stored thereon, the computer program comprising:

instructions operable to cause a processor to control operation of a delay-locked loop circuitry, wherein said delay-locked loop circuitry is configured to trigger generation of first-type edges of a target signal for use with a digital pulse-width modulator in a digital feedback loop of a switched-mode power supply, and wherein operation of the delay-locked loop circuitry is controlled in a way that said delay-locked loop circuitry is turned on before generation of each first-type edge of said target signal and turned off after generation of each said first-type edge, wherein said delay-locked loop circuitry is configured to trigger generation of said first-type edges of said target signal at least partially based on a first clock signal, wherein said delay-locked loop circuitry comprises:

a delay-locked loop configured to output a plurality of delayed representations of said first clock signal, and

a combination circuitry configured to combine said plurality of delayed representations of said first clock signal into a signal via which said delay-locked loop circuitry triggers generation of said first-type edges of said target signal, wherein an operation of said combination circuitry is controlled by a main control circuitry, wherein said delay-locked loop comprises:

a switch configured to receive a representation of said first clock signal;

a line of delay elements connected to an output of said switch, wherein said delay elements in said line of delay elements generate said plurality of delayed representations of said first clock signal;

a phase detector configured to control said delay elements based on a comparison of two different representations of said first clock signal, and

a switch and phase detector control circuitry configured to control operation of said switch of said delay-locked loop and to turn on and off said phase detector of said delay-locked loop in response to at least one control signal generated by said main control circuitry.

21. The computer-readable medium of claim 20 , wherein said target signal is a pulse-width modulated signal, and wherein said computer-readable medium further comprises:

instructions operable to control a switching circuitry of a switched-mode power supply at least partially based on said pulse-width modulated signal.

Assignments (9)