System and method for verifying the receive path of an input/output component
View Patent ↗A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process.
1. A verification environment for verifying operation of the receive path of an input/output device, the verification environment comprising:
a software model of the input/output device;
a host configured to receive data through the input/output device;
a verification layer configured to model receipt of packets containing the data through the input/output device, wherein the verification layer comprises:
a set of port queues corresponding to input ports of the input/output device, wherein the port queues are populated with tokens representing the packets;
a queue for each DMA (Direct Memory Access) engine of the input/output device; and
an address generator configured to generate addresses at which the input/output device is expected to store data from the packets; and
a receive checker configured to compare an output of the input/output device with an output modeled by the verification layer.
2. The verification environment of claim 1 , wherein said verification layer further comprises:
a DMA status register configured to maintain a status of a DMA engine of the input/output device.
3. The verification environment of claim 1 , wherein said verification environment further comprises:
a host abstraction layer configured to enable the verification layer to communicate with receive checkers corresponding to different types of hosts; and
a network abstraction layer configured to enable the verification layer to receive input data from different types of networks.
4. A computer-implemented method of verifying a receive path of an input/output device, the method comprising:
operating a software model of the input/output device;
operating a verification layer configured to model receipt of packets through the input/output device;
operating a network abstraction layer configured to interface the verification layer with a data network from which the input/output device is configured to receive the packets, wherein the verification layer can interact with any of multiple different network abstraction layers;
operating a host abstraction layer configured to interface the verification layer with a destination of the packets, wherein the verification layer can interact with any of multiple different host abstraction layers;
associating call backs with packets received from a data input source;
resolving the call backs as the packets' data are written to the destination;
modeling processing of the packets' data within the input/output device as call backs associated with the packets are resolved; and
predicting storage locations of the packets' data by the input/output device based on resolution of the call backs.
5. A computer-implemented method of verifying a receive path of an input/output device, the method comprising:
configuring a verification environment comprising a model of the input/output device, a verification layer for verifying operation of the model and an input source for modeling input of packets to the input/output device from a network;
generating a set of attributes for a packet;
formatting the packet based on the set of attributes;
submitting the packet to the input/output device for processing;
in parallel with said submitting, generating a token within the verification layer to represent the packet;
identifying within the verification layer a memory area where the input/output device should store the packet on a host;
generating a call back to determine when requested data has been stored on the host; and
comparing output modeled by the verification layer with output of the input/output device to determine whether the input/output device stored the packet correctly.
6. The method of claim 5 , further comprising:
maintaining port queues in the verification layer to model ports of the input/output device;
wherein the port queues are populated with tokens representing packets input to the input/output device.
7. The method of claim 5 , further comprising:
maintaining DMA (Direct Memory Access) queues in the verification layer to model operation of DMA engines within the input/output device.
8. The method of claim 5 , wherein said call back comprises monitoring the identified memory area to determine whether the packet is stored in the memory area.
9. The method of claim 5 , further comprising:
implementing in the input/output device an initial DMA policy for the handling of packets;
modeling the initial policy within the verification layer;
identifying a replacement policy; and
dynamically replacing the initial policy with the replacement policy without halting the verification.
10. A computer readable medium storing instructions that, when executed by a computer, cause the computer to perform a method of verifying a receive path of an input/output device, the method comprising:
configuring a verification environment comprising a model of the input/output device, a verification layer for verifying operation of the model and an input source for modeling input of packets to the input/output device from a network;
generating a set of attributes for a packet;
formatting the packet based on the set of attributes;
submitting the packet to the input/output device for processing;
generating a token within the verification layer to represent the packet;
calculating within the verification layer where the input/output device should store the packet on a host;
generating a call back to determine when requested data has been stored on the host; and
comparing output modeled by the verification layer with output of the input/output device to determine whether the input/output device stored the packet correctly.