Field effect transistor formed on an insulating substrate and integrated circuit thereof
View Patent ↗A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation.
1. A field effect transistor formed on an insulating substrate, comprising:
an insulating substrate;
a semiconductor thin film formed on the insulating substrate;
a gate insulating film provided on the semiconductor thin film;
a first gate electrode having a length and a width and being formed on the gate insulating film;
a first region and a second region having a first conductivity type and being formed on or in the surface of the semiconductor thin film on opposite sides of the first gate electrode in the length direction thereof;
a third region having a second conductivity type opposite the first conductivity type and being arranged side by side with the second region in the width direction of the first gate electrode;
the third region and the second region being in contact with each other and making a low resistance junction, and the third region and the second region not being connected together via metal wiring and contact holes;
a second gate electrode having a length and a width and being formed on the gate insulating film along the second and third regions; and
a fourth region having the first conductivity type and being formed on or in the surface of the semiconductor thin film and on an opposite side of the second region with respect to the second gate electrode in a length direction thereof, one of the first and the fourth regions being used as an output region without any fixed bias potential to the third region according to a bi-directional circuit operation of the field effect transistor.
2. A field effect transistor according to claim 1 ; including a plurality of second regions and a plurality of third regions, the second regions being alternately arranged with respect to the third regions in the width direction of the first gate electrode.
3. A field effect transistor according to claim 2 ; wherein a distance between adjacent third regions is set to be no more than 50 times as large as a channel length of the field effect transistor.
4. A field effect transistor according to claim 2 ; wherein a distance between adjacent third regions is set to be no more than 10 times as large as a channel length of the field effect transistor.
5. A field effect transistor according to claim 1 ; wherein the first and the fourth regions each have a portion with a relatively low impurity concentration and a portion with a relatively high impurity concentration, the portion with a relatively low impurity concentration being arranged closer to the first or the second gate electrode than the portion with a relatively high impurity concentration.
6. A field effect transistor formed on an insulating substrate according to claim 1 ; wherein the insulating substrate is made of an insulating material selected from the group consisting of glass, sapphire, and ceramic.
7. A field effect transistor formed on an insulating substrate according to claim 1 ; wherein the insulating substrate has an insulating film formed on a silicon substrate.
8. A field effect transistor formed on an insulating substrate according to claim 1 ; wherein the third region and the second region are each doped with 1×10 19 atoms/cc or more.
9. A field effect transistor formed on an insulating substrate according to claim 1 ; wherein the third region is formed of a silicide or metal thin film, which partially contacts with the second region, and the impurity concentration of the second region is 1×10 19 atoms/cc or more near the junction with the third region.
10. A field effect transistor formed on an insulating substrate according to claim 1 ; wherein a width of the second region is set as no more than 25 times as large as a channel length of the field effect transistor.