High electron mobility transistor semiconductor device having field mitigating plate and fabrication method thereof
View Patent ↗A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.
1. A semiconductor device comprising:
a semi-insulating substrate;
a channel layer disposed above the semi-insulating substrate;
a barrier layer disposed over the channel layer, the barrier layer inducing a 2-DEG layer at an interface between the barrier layer and the channel layer;
source and drain regions disposed above the barrier layer to form a low resistivity connection through the barrier layer to the 2-DEG layer;
a T-gate disposed between the source and drain regions and above the barrier layer;
a first field plate disposed above a portion of the T-gate;
a second field plate disposed above the barrier layer and in a vicinity of the T-gate; and
a dielectric layer coating a portion of the barrier layer between the source region and the T-gate and between the drain region and the T-gate, and the T-gate,
wherein the first and second field plates are disposed on the dielectric layer.
2. The semiconductor device of claim 1 , wherein the second field plate is connected to one of the source region and the T-gate.
3. The semiconductor device of claim 1 , wherein the dielectric layer comprises silicon nitride (SiN).
4. The semiconductor device of claim 1 , wherein a lateral length of the second field plate is between 0.15 and 0.20 micrometers.
5. The semiconductor device of claim 1 , wherein a lateral length of the second field plate is less than or equal to 0.15 micrometers.
6. The semiconductor device of claim 1 ,
wherein the T-gate layer includes a relatively wide wing portion on top and a relatively thin gate stem portion on bottom,
wherein the first field plate disposed above the wing portion of the T-gate, and
wherein the gate stem portion is formed above the entire barrier layer.
7. The semiconductor device of claim 6 ,
wherein a first thickness of the first field plate is less than a height of the gate stem portion of the T-gate, and
wherein a second thickness of the second field plate is less than the height of the gate stem portion of the T-gate.
8. The semiconductor device of claim 1 ,
wherein the first field plate is larger than the second field plate.
9. The semiconductor device of claim 1 ,
wherein the second field plate is connected to either the source region or the T-gate.