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App. No. 11/976,789 · Confirmation No. 3846

Power consumption optimizing method for semiconductor integrated circuit and semiconductor designing apparatus

Inventor: Jun Yamada
Abandoned -- Failure to Respond to an Office Action View Publication ↗
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2010-10-14 ABN Abandonment 2 View
2010-04-01 CTRS Requirement for Restriction/Election 2 View
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2007-10-29 PD.REQ.RETR Request for USPTO to retrieve priority docs 2 View
2007-10-29 A.PE Preliminary Amendment 1 View
2007-10-29 SPEC Specification 1 View
2007-10-29 REM Applicant Arguments/Remarks Made in an Amendment 1 View
2007-10-29 TRNA Transmittal of New Application 2 View
2007-10-29 SPEC Specification 20 View
2007-10-29 CLM Claims 3 View
2007-10-29 ABST Abstract 1 View
2007-10-29 DRW Drawings-only black and white line drawings 4 View
2007-10-29 OATH Oath or Declaration filed 3 View
2007-10-29 FRPR Certified Copy of Foreign Priority Application 1 View
2007-10-29 TRAN.LET Transmittal Letter 2 View
2007-10-29 IDS Information Disclosure Statement (IDS) Form (SB08) 1 View
2007-10-29 FOR Foreign Reference 18 View
2007-10-29 WFEE Fee Worksheet (SB06) 1 View
2007-10-29 WFEE Fee Worksheet (SB06) 1 View
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Quick Facts
App. No.
11/976,789
Filed
2007-10-29
Pub. No.
US20080104552A1
Art Unit
2825