PC-based computing system employing a bridge chip having a routing unit, a control unit and a profiling unit for parallelizing the operation of multiple GPU-driven pipeline cores according to the object division mode of parallel operation
A PC-based computing system employing a bridge chip having a routing unit, a control unit and profiling unit for parallelizing multiple GPU-driven pipeline cores according to the object division mode of parallelization operation, during a graphics application. The PC-based computing system includes system memory for storing software graphics applications, software drivers and graphics libraries, and an operating system (OS), stored in the system memory, and a central processing unit (CPU), for executing the OS, graphics applications, drivers and graphics libraries. The routing unit (i) routes the stream of geometrical data and graphic commands from the CPU to one or more of the GPU-driven pipeline cores, and (ii) routes pixel data output from one or more of GPU-driven pipeline cores during the composition of frames of pixel data corresponding to final images for display on the display surface. The control unit accepts commands from the software multi-pipe drivers, and controls components within the bridge chip, including the routing unit. The profiling unit profiles the performance of the GPU-driven pipeline cores and feeds back performance data to the software multi-pipe drivers, for balancing the data load among the GPU-driven pipeline cores during the object division mode of parallelization operation.
1 . A PC-based computing system comprising:
system memory for storing software graphics applications, software drivers and graphics libraries, and;
an operating system (OS), stored in said system memory;
one or more graphics applications, stored in said system memory, for generating a stream of geometrical data and graphics commands supporting (i) the representation of one or more 3D objects in a scene having 3D geometrical characteristics and (ii) the viewing of images of said one or more 3D objects in said scene;
one or more graphic libraries, stored in said system memory, for storing data used to implement said stream of geometrical data and graphics commands;
a central processing unit (CPU) supported on a motherboard, for executing said OS, said graphics applications, said drivers and said graphics libraries;
a CPU bus supported on said motherboard;
a display surface for displaying said images by graphically displaying frames of pixel data;
a bridge chip having a routing unit, and a control unit;
a plurality of GPU-driven pipeline cores arranged in a parallel architecture and operating according to a parallelization mode of operation so that said GPU-driven pipeline cores process data in a parallel manner; and
software multi-pipe drivers, stored in said system memory, and including a GPU driver module allowing said GPU-driven pipeline cores to interact with said OS and said graphic libraries, and a distributed graphic functions control module for configuring said parallelization mode of operation;
wherein said routing unit located on said CPU bus and interfacing said CPU and said GPU-driven pipeline cores;
wherein said control unit accepts commands from said software multi-pipe drivers, over said CPU bus, and controls components within said bridge chip, including said routing unit;
wherein said profiling unit profiles the performance of said GPU-driven pipeline cores and feeds back performance data to said software multi-pipe drivers, for balancing the data load among said GPU-driven pipeline cores during said object division mode of parallelization operation;
wherein, for each image of said 3D object to be generated and displayed on said display surface, the following operations are performed:
(i) said routing unit routes said stream of geometrical data and graphic commands, or a portion thereof, from said CPU to one or more of said GPU-driven pipeline cores,
(ii) one or more of said GPU-driven pipeline cores process said stream of geometrical data and graphic commands, or a portion thereof, during the generation of each said frame, while operating in said parallelization mode, so as to generate pixel data corresponding to at least a portion of said image, and
(iii) said routing unit routes pixel data output from one or more of said GPU-driven pipeline cores during the composition of each frames of pixel data corresponding to a final image, for display on said display surface.
2 . The PC-based computing system of claim 1 , wherein said bridge chip further comprises a memory unit for storing intermediate processing results from one or more of said multiple GPU-driven pipeline cores, and data required for composition and transferring frames of pixel data for display.
3 . The PC-based computing system of claim 1 , wherein during said object division mode of parallelization operation, the 3D object which is to be displayed as an image consisting of a frame of pixels, is decomposed into said stream of geometrical data and graphic commands which are distributed to said GPU-driven pipeline cores for rendering the frames of pixel data compositing the images to be displayed on said display surface.
4 . The PC-based computing system of claim 1 , wherein each said 3D object is decomposable into a plurality of polygons, and wherein said geometrical data comprises the vertices of said polygons.
5 . The PC-based computing system of claim 1 , wherein each said GPU-driven pipeline core has a frame buffer (FB) for storing a fragment of pixel data.
6 . The PC-based computing system of claim 1 , wherein said geometrical data comprises a set of scene polygons, textures and vertex objects.
7 . The PC-based computing system of claim 1 , wherein said graphics commands includes commands selected from the group consisting of display lists and display vertex arrays.
8 . The PC-based computing system of claim 1 , wherein said graphic libraries are selected from the group consisting of OpenGL and DirectX.
9 . The PC-based computing system of claim 1 , wherein each pixel associated with a frame of pixel data includes attributes selected from the group consisting of color, alpha, position, depth, and stencil.
10 . The PC-based computing system of claim 1 , wherein each said 3D object is decomposable into a plurality of polygons, and wherein said geometrical data comprises the vertices of said polygon
11 . The PC-based computing system of claim 1 , wherein said bridge chip is a memory bridge chip, and said bridge chip also interfaces with said system memory.
12 . The PC-based computing system of claim 1 , wherein said plurality of GPU-driven pipeline cores are supported on said bridge chip, and wherein said bridge chip further comprises a display interface for interfacing said display surface with at least one of said GPU-driven pipeline core.
13 . The PC-based computing system of claim 13 , wherein said bridge chip is realized as a multi-processor (MP) system-on-a-chip (MP-SOC) architecture.
14 . The PC-based computing system of claim 1 , which further comprises a graphics card with a display interface for interfacing with said display surface, and wherein said plurality of GPU-driven pipeline cores are mounted on said graphics card.
15 . The PC-based computing system of claim 1 , which further comprises a graphics card with a display interface for interfacing with said display surface, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on said graphics card, and at least one of said plurality of GPU-driven pipeline cores is supported on said bridge chip.
16 . The PC-based computing system of claim 1 , which further comprises a graphics card with a display interface for interfacing with said display surface, and wherein two or more of said plurality of GPU-driven pipeline cores are supported on said graphics card, and at least one of said plurality of GPU-driven pipeline cores is supported on said bridge chip.
17 . The PC-based computing system of claim 1 , which further comprises first and second graphics cards, with said first graphics card having a display interface for interfacing with said display surface, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on said first graphics card, and at least one of said plurality of GPU-driven pipeline cores is supported on said second graphics card.
18 . The PC-based computing system of claim 1 , which further comprises first and second graphics cards, with said first graphics card having a display interface for interfacing with said display surface, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on said first graphics card, wherein at least one of said plurality of GPU-driven pipeline cores is supported on said second graphics card, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on said bridge chip.
19 . The PC-based computing system of claim 1 , which further comprises plurality of graphics cards, with one of said plurality of graphics card having a display interface for interfacing with said display surface, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on each said graphics card.
20 . The PC-based computing system of claim 1 , which further comprises plurality of graphics cards, with one of said plurality of graphics card having a display interface for interfacing with said display surface, wherein at least one of said plurality of GPU-driven pipeline cores is supported on each said graphics card, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on said bridge chip.