PC-based computing system employing a bridge chip implementing parallelized GPU-driven pipelines cores supporting multiple modes of parallelization dynamically controlled while running a graphics application

1 . A PC-based computing system comprising:

system memory for storing software graphics applications, software drivers and graphics libraries, and;

an operating system (OS), stored in said system memory;

one or more graphics applications, stored in said system memory, for generating a stream of geometrical data and graphics commands supporting (i) the representation of one or more 3D objects in a scene having 3D geometrical characteristics and (ii) the viewing of images of said one or more 3D objects in said scene;

one or more graphic libraries, stored in said system memory, for storing data used to implement said stream of geometrical data and graphics commands;

a central processing unit (CPU) supported on a motherboard, for executing said OS, said graphics applications, said drivers and said graphics libraries;

a CPU bus supported on said motherboard;

a display surface for displaying said images by graphically displaying frames of pixel data;

a bridge chip having a routing unit, a control unit, and profiling unit;

a plurality of GPU-driven pipeline cores arranged in a parallel architecture and operating according to one or more parallelization modes of operation, determined during the generation of each said frame of pixel data, so that said GPU-driven pipeline cores process data in a parallel manner; and

software multi-pipe drivers, stored in said system memory, and including (i) a first software module allowing said GPU-driven pipeline cores to interact with said OS and said graphic libraries, (ii) a second software module for configuring said parallelization mode of operation, (iii) a third software module for continuous profiling and analyzing said graphics application, and (iv) a fourth software module for dynamically determining and controlling said parallelization mode during the generation of each said frame of pixel data during the running of said graphics application;

wherein said routing unit located on said CPU bus and interfacing said CPU and said GPU-driven pipeline cores;

wherein said control unit accepts commands from said software multi-pipe drivers, over said CPU bus, and controls components within said bridge chip, including said routing unit;

wherein said profiling unit profiles the performance of said GPU-driven pipeline cores and feeds back performance data to said software multi-pipe drivers, for balancing the data load among said GPU-driven pipeline cores during said parallelization mode of operation;

wherein, for each image of said 3D object to be generated and displayed on said display surface, the following operations are performed:

(i) said routing unit routes said stream of geometrical data and graphic commands, or a portion thereof, from said CPU to one or more of said GPU-driven pipeline cores,

(ii) one or more of said GPU-driven pipeline cores process said stream of geometrical data and graphic commands, or a portion thereof, during the generation of each said frame, while operating in said parallelization mode, so as to generate pixel data corresponding to at least a portion of said image, and

(iii) said routing unit routes pixel data output from one or more of said GPU- driven pipeline cores during the composition of each frames of pixel data corresponding to a final image, for display on said display surface.

2 . The PC-based computing system of claim 1 , wherein said bridge chip further comprises a memory unit for storing intermediate processing results from one or more of said multiple GPU-driven pipeline cores, and data required for composition and transferring frames of pixel data for display.

3 . The PC-based computing system of claim 1 , wherein each said GPU-driven pipeline core has a frame buffer (FB) for storing a fragment of pixel data.

4 . The PC-based computing system of claim 1 , wherein said geometrical data comprises a set of scene polygons, textures and vertex objects.

5 . The PC-based computing system of claim 1 , wherein said graphics commands includes commands selected from the group consisting of display lists and display vertex arrays.

6 . The PC-based computing system of claim 1 , wherein said graphic libraries are selected from the group consisting of OpenGL and DirectX.

7 . The PC-based computing system of claim 1 , wherein when said parallelization mode of operation is said time division mode, each said GPU renders a different frame of pixel data for display on said display surface at a different moment of time.

8 . The PC-based computing system of claim 1 , wherein when said parallelization mode of operation is said image division mode, each GPU renders a subset of the pixels used to compose each frame of pixel data to be displayed on said display surface.

9 . The PC-based computing system of claim 1 , wherein when said parallelization mode of operation is said object division mode, the 3D object which is to be displayed as an image consisting of a frame of pixels, is decomposed into said stream of geometrical data and graphic commands which are distributed to said GPU-driven pipeline cores for rendering the frames of pixel data compositing the images to be displayed on said display surface.

10 . The PC-based computing system of claim 9 , wherein each said 3D object is decomposable into a plurality of polygons, and wherein said geometrical data comprises the vertices of said polygons.

11 . The PC-based computing system of claim 1 , wherein said software multi-pipe drivers further comprise one or more of the following software modules installed in said system memory:

a fifth software module for continuously analyzing substantially all incoming commands, including state commands, transferring certain state commands and some of the data all of said GPU-driven pipeline cores so as to preserve the valid state across said GPU-driven graphic pipeline cores.

12 . The PC-based computing system of claim 1 , wherein said third software modules uses inputs from (i) the registers of said multiple GPU-driven pipeline cores, and (ii) registers of said control unit, and graphic API commands.

13 . The PC-based computing system of claim 1 , wherein said dynamically determining and controlling said parallelization mode during any particular frame of pixel data generation and display is based on factors including the time required to render previous frames of pixel data and bottlenecks exhibited in vertex processing and pixel processing during the rendering of said previous frames of pixel data.

19 . The PC-based computing system of claim 1 , wherein said parallelization mode operation is based on any combination of said object division mode, said image division mode and said time division mode.

20 . The PC-based computing system claim 1 , wherein said fourth software module analyzes collected parameters including data selected from the group consisting of: memory speed, memory usage in bytes, total pixels rendered, geometric data entering rendering, frame rate, workload of each pipeline core, load balance among graphic pipelines, volumes of transferred data, textures count, and depth complexity.

21 . The PC-based computing system claim 1 , wherein the number of said GPU-driven pipeline cores has no architectural limit.

22 . The PC-based computing system of claim 1 , wherein said bridge chip is a memory bridge chip, and said bridge chip also interfaces with said system memory.

23 . The PC-based computing system of claim 1 , wherein said plurality of GPU-driven pipeline cores are supported on said bridge chip, and wherein said bridge chip further comprises a display interface for interfacing said display surface with at least one of said GPU-driven pipeline core.

24 . The PC-based computing system of claim 1 , wherein said bridge chip is realized as a multi-processor (MP) system-on-a-chip (MP-SOC) architecture.

25 . The PC-based computing system of claim 1 , which further comprises a graphics card with a display interface for interfacing with said display surface, and wherein said plurality of GPU-driven pipeline cores are mounted on said graphics card.

26 . The PC-based computing system of claim 1 , which further comprises a graphics card with a display interface for interfacing with said display surface, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on said graphics card, and at least one of said plurality of GPU-driven pipeline cores is supported on said bridge chip.

27 . The PC-based computing system of claim 1 , which further comprises a graphics card with a display interface for interfacing with said display surface, and wherein two or more of said plurality of GPU-driven pipeline cores are supported on said graphics card, and at least one of said plurality of GPU-driven pipeline cores is supported on said bridge chip.

28 . The PC-based computing system of claim 1 , which further comprises first and second graphics cards, with said first graphics card having a display interface for interfacing with said display surface, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on said first graphics card, and at least one of said plurality of GPU-driven pipeline cores is supported on said second graphics card.

29 . The PC-based computing system of claim 1 , which further comprises first and second graphics cards, with said first graphics card having a display interface for interfacing with said display surface, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on said first graphics card, wherein at least one of said plurality of GPU-driven pipeline cores is supported on said second graphics card, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on said bridge chip.

30 . The PC-based computing system of claim 1 , which further comprises plurality of graphics cards, with one of said plurality of graphics card having a display interface for interfacing with said display surface, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on each said graphics card.

31 . The PC-based computing system of claim 1 , which further comprises plurality of graphics cards, with one of said plurality of graphics card having a display interface for interfacing with said display surface, wherein at least one of said plurality of GPU-driven pipeline cores is supported on each said graphics card, and wherein at least one of said plurality of GPU-driven pipeline cores is supported on said bridge chip.