Semiconductor integrated circuit and design method for semiconductor integrated circuit
View Patent ↗The semiconductor integrated circuit of the invention includes: two first power supply lines placed in parallel in a same interconnect layer; a second power supply line placed between the two first power supply lines in the same interconnect layer; an actual operation flipflop connected to one of the two first power supply lines and the second power supply line and having a first clock terminal; and a dummy flipflop connected to the other first power supply line and the second power supply line and having a second clock terminal. The dummy flipflop includes: a contact connected to the other first power supply line or the second power supply line; and an interconnect for connecting the second clock terminal with the contact.
1. A semiconductor integrated circuit comprising:
a power supply line;
a ground line placed in a same interconnect layer as the power supply line;
an actual operation flipflop connected to the power supply line and the ground line, the actual operation flipflop having a first clock terminal; and
a dummy flipflop connected to the power supply line and the ground line, the dummy flipflop having a second clock terminal,
wherein the dummy flipflop comprises:
a contact connected to the power supply line or the ground line; and
an interconnect for connecting the second clock terminal with the contact, and
is placed so that the distance between the first clock terminal and the second clock terminal in the direction of extension of the ground line is shorter than the length of the actual operation flipflop in the direction of extension of the ground line.
2. The circuit of claim 1 , wherein the actual operation flipflop and the dummy flipflop are adjacent to each other.
3. The circuit of claim 1 , further comprising a circuit modification interconnect extending from the first clock terminal toward the second clock terminal.
4. The circuit of claim 1 , further comprising:
at least one contact for first stack;
at least one interconnect for first stack stacked alternately with the at least one contact for first stack on the power supply line or the ground line;
at least one contact for second stack;
at least one interconnect for second stack stacked alternately with the at least one contact for second stack on the second clock terminal; and
an interconnect for connecting one of the at least one contact for first stack with one of the at least one contact for second stack, both the contacts being placed in a same layer.
5. The circuit of claim 1 , further comprising:
at least one contact for stack; and
at least one interconnect for stack stacked alternately with the at least one contact for stack on the power supply line or the ground line.