IP Library Granted Patent US 7,956,829
Granted Patent B2
US 7,956,829 · App. 11/979,653 · Granted Jun 7, 2011

Display apparatus

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Quick Facts
Patent No.
US 7,956,829
App. No.
11/979,653
Granted
Jun 7, 2011
Kind
B2
Abstract

Disclosed herein is a display apparatus includes, a pixel array and a driver configured to drive the pixel array. The pixel array includes rows of scanning lines, columns of signal lines, a matrix of pixels disposed at crossings of the scanning lines and the signal lines, and feeding lines associated with respective rows of the pixels, the pixels including respective sampling transistors having respective gates connected to the scanning lines; and the driver includes a main scanner configured to supply control signals to the scanning lines, the main scanner including a shift register, output buffers connected respectively between the shift register and the scanning lines, and a pulse power supply configured to supply power supply pulses, each having a predetermined pulse duration, to the output buffers, and wherein the main scanner outputs power supply pulses supplied from the pulse power supply as the control signals to the respective scanning lines in response to a shift pulse output from the shift register.

Claims (25)

1. A display apparatus comprising:

a pixel array; and

a driver configured to drive said pixel array;

wherein said pixel array including rows of scanning lines, columns of signal lines, and a matrix of pixels disposed at crossings of said scanning lines and the signal lines,

said driver including a main scanner configured to supply control signals to said scanning lines,

said main scanner including a shift register, output buffers connected respectively between said shift register and said scanning lines, and a pulse power supply

wherein each of said output buffers comprises an inverter including a pair of complementary switching devices connected in series between a power supply line and a ground line, and said pulse power supply supplies a train of power supply pulses to the power supply line of said inverter.

2. The display apparatus according to claim 1 ,

wherein each of said pixels comprises a light-emitting element, a driving transistor, and a retentive capacitor;

said sampling transistor having a source and a drain, one of which is connected to one of said signal lines and the other to the gate of the driving transistor;

said driving transistor having a source and a drain, one of which is connected to said light-emitting element and the other to one of said feeding lines; and

said retentive capacitor being connected between the source and the gate of the driving transistor;

wherein when a signal potential is held in said retentive capacitor, said main scanner renders said sampling transistor conductive to electrically disconnect the gate of said driving transistor from the signal line.

3. The display apparatus according to claim 1 , wherein said pixels comprise respective driving transistor and respective retentive capacitors, said driver includes a power supply scanner configured to switch said feeding lines from a first potential to a second potential at a first timing before said sampling transistors sample signal potentials;

said main scanner renders said sampling transistors conductive to apply a reference potential from said signal lines to the gates of said driving transistors at a second timing before said sampling transistors sample signal potentials; and

said power supply scanner switches said feeding lines from the second potential to the first potential to hold a voltage corresponding to a threshold voltage of said driving transistors in said retentive capacitors at a third timing after said second timing.

4. The display apparatus according to claim 1 , wherein at least one of said switching devices which is closer to said power supply line comprises a transmission gate device.

5. A display apparatus comprising:

a pixel array; and

a driver configured to drive said pixel array;

wherein said pixel array including rows of scanning lines, columns of signal lines, and a matrix of pixels disposed at crossings of said scanning lines and the signal lines, and feeding lines associated with respective rows of the pixels, said pixels including respective sampling transistors having respective gates connected to said scanning lines,

said driver including a main scanner configured to supply control signals to said scanning lines,

said main scanner including a shift register, output buffers connected respectively between said shift register and said scanning lines, and a pulse power supply configured to supply power supply pulses, each having a predetermined pulse duration, to said output buffers, wherein said main scanner outputs power supply pulses supplied from said pulse power supply as the control signals to the respective scanning lines in response to a shift pulse output from said shift register, and

wherein each of said output buffers comprises an inverter including a pair of complementary switching devices connected in series between a power supply line and a ground line, and said pulse power supply supplies a train of power supply pulses to the power supply line of said inverter.

6. The display apparatus according to claim 5 , wherein at least one of said switching devices which is closer to said power supply line comprises a transmission gate device.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2015
From: SONY CORPORATION
To: JOLED INC.
Reel/Frame 036106/0355 →