Semiconductor integrated circuit and multi-chip module
View Patent ↗In a semiconductor integrated circuit requiring a large number of pads, an internal circuit is arranged in the center portion, and a plurality of two kinds of I/O circuits for inputting and outputting signals from and to the outside and many pads are arranged along four sides of the semiconductor integrated circuit. The plurality of I/O circuits that are of one of the foregoing two kinds are one-pad I/O circuits on which one pad is arranged in a direction toward the internal circuit, whereas the plurality of I/O circuits that are of the other of the foregoing two kinds are two-pad I/O circuits on which two pads are arranged in zigzag relationship in a direction toward the internal circuit. The number of arranged pads equals to the number of pads required for the semiconductor integrated circuit. The one-pad I/O circuits and the two-pad I/O circuits are provided with power source wirings for supplying power thereto. The power source wirings extend along the arrangement direction of the one-pad I/O circuits and the second-pad I/O circuits to be ring-shaped. power source wiring migration areas for changing power source wirings between the one-pad I/O circuits and second-pad I/O circuits are disposed in four corner portions of the semiconductor integrated circuit.
1. A semiconductor integrated circuit, comprising:
an internal circuit; and
a plurality of input/output (I/O) circuits that are arranged side by side outside the internal circuit, that output a signal of the internal circuit to outside or input a signal of outside to the internal circuit, and on which pads are arrangeable,
the plurality of I/O circuits including at least two kinds of I/O circuit differing in height in a direction toward the internal circuit, the at least two kinds of I/O circuit including:
an n-pad I/O circuit on which the n-pads (n being an integer equal to or larger than one) are arranged in a direction toward the internal circuit, and
an m-pad I/O circuit on which the m-pads (m being an integer larger than n) are arranged in a direction toward the internal circuit,
wherein:
each of the n-pad I/O circuit and the m-pad I/O circuit includes power source wirings extending in a direction of arrangement of the I/O circuits, and at least one of the power source wirings is positioned at a different height from an outer edge between the n-pad I/O circuit and the m-pad I/O circuit; and
between the n-pad I/O circuit and the m-pad I/O circuit arranged side by side, a power source wiring migration area is formed in which power source wirings for connecting the power source wirings of the n-pad I/O circuit with the power source wirings of the m-pad I/O circuit are formed.
2. The semiconductor integrated circuit according to claim 1 , wherein:
the n-pad I/O circuit and the m-pad I/O circuit are positioned in ends of two sides that form a corner portion of the semiconductor integrated circuit; and
the power source wiring migration area is formed in the corner portion.
3. The semiconductor integrated circuit according to claim 1 , wherein the power source wirings included in the n-pad I/O circuit and the power source wirings included in the m-pad I/O circuit differ from each other in number.
4. The semiconductor integrated circuit according to claim 1 , wherein the power source wirings included in the n-pad I/O circuit and the power source wirings included in the m-pad I/O circuit differ from each other in wiring width.
5. The semiconductor integrated circuit according to claim 1 , wherein a wiring layer in which the power source wirings included in the n-pad I/O circuit are formed and a wiring layer in which the power source wirings included in the m-pad I/O circuit are formed differ from each other.
6. The semiconductor integrated circuit according to claim 1 , wherein a wiring layer in which the power source wirings included in the n-pad I/O circuit are formed and a wiring layer in which the power source wirings included in the m-pad I/O circuit are formed differ from each other in number.
7. The semiconductor integrated circuit according to claim 1 , wherein:
the semiconductor integrated circuit is a rectangle having four sides;
same kind of I/O circuits, which are either the n-pad I/O circuits or the m-pad I/O circuits, are arranged along one pair of sides of two pairs of sides facing each other; and
I/O circuits different in pad number from either the n-pad I/O circuits or the m-pad I/O circuits arranged along the one pair of sides are arranged along one side of another pair of sides.
8. The semiconductor integrated circuit according to claim 1 , wherein:
a plurality of n-pad I/O circuits are arranged side by side along one side of the semiconductor integrated circuit; and
an arrangement pitch of the plurality of n-pad I/O circuits arranged side by side along the one side is set in consideration of an arrangement pitch of a plurality of I/O circuits arranged along one side of another semiconductor integrated circuit.
9. The semiconductor integrated circuit according to claim 1 , wherein:
a plurality of n-pad I/O circuits and a plurality of m-pad I/O circuits are arranged side by side; and
on an entirety of the plurality of n-pad I/O circuits and the plurality of m-pad I/O circuits, a plurality of pads are arranged in a direction toward the internal circuit, a multiplicity of pads arranged in the plurality of n-pad I/O circuits are arranged in zigzag relationship, and a multiplicity of pads arranged in the plurality of m-pad I/O circuits are arranged in zigzag relationship.
10. The semiconductor integrated circuit according to claim 1 , wherein on an entirety of the included n-pad I/O circuits and the m-pad I/O circuits, a total number of pads positioned in a predetermined row and a total number of pads positioned in a row numbered one more than the predetermined row differ from each other.
11. The semiconductor integrated circuit according to claim 1 , wherein the n-pad I/O circuit and the m-pad I/O circuit differ from each other in width in an arrangement direction.
12. The semiconductor integrated circuit according to claim 1 , wherein total gate widths of transistors each having a drain connected directly to a pad are equal to each other between the n-pad I/O circuit and the m-pad I/O circuit.
13. The semiconductor integrated circuit according to claim 1 , wherein gate lengths of transistors that realize a same function are equal to each other between the n-pad I/O circuit and the m-pad I/O circuit.
14. The semiconductor integrated circuit according to claim 1 , wherein gate widths of transistors that realize a same function are equal to each other between the n-pad I/O circuit and the m-pad I/O circuit.
15. The semiconductor integrated circuit according to claim 1 , wherein:
a width of the n-pad circuit in a direction of arrangement of the n-pad I/O circuits is larger than a width of the m-pad circuit in a direction of arrangement of the m-pad I/O circuits; and
a height in the direction toward the internal circuit of the n-pad I/O circuit is less than a height in the direction toward the internal circuit of the m-pad I/O circuit.
16. A multi-chip module, comprising:
a semiconductor chip constituting the semiconductor integrated circuit according to claim 8 ; and
a semiconductor chip constituting another semiconductor integrated circuit,
wherein the plurality of n-pad I/O circuits arranged along the one side of the semiconductor integrated circuit according to claim 11 and a plurality of I/O circuits arranged along one side of the another semiconductor integrated circuit face each other and are connected by a chip-to-chip interconnect.
17. The semiconductor integrated circuit according to claim 12 , wherein in the n-pad I/O circuit and the m-pad I/O circuit:
transistors of a same conductive type each having a drain connected directly to a pad are in multifinger structures; and
gate widths are equal to each other between the multifinger structures.
18. A semiconductor integrated circuit, comprising:
an internal circuit; and
a plurality of input/output (I/O) circuits that are arranged side by side outside the internal circuit, that output a signal of the internal circuit to outside or input a signal of outside to the internal circuit, and on which pads are arrangeable,
the plurality of I/O circuits including at least two kinds of I/O circuit differing in height in a direction toward the internal circuit, the at least two kinds of I/O circuit including:
an n-pad I/O circuit on which the n-pads (n being an integer equal to or larger than one) are arranged in a direction toward the internal circuit, and
an m-pad I/O circuit on which the m-pads (m being an integer larger than n) are arranged in a direction toward the internal circuit,
wherein:
each of the n-pad I/O circuit and the m-pad I/O circuit includes power source wirings extending in a direction of arrangement of the I/O circuits, and at least one of the power source wirings is positioned at a different height from an outer edge between the n-pad I/O circuit and the m-pad I/O circuit; and
the n-pad I/O circuit and the m-pad I/O circuit arranged side by side adjacent to each other are positioned apart from each other by a predetermined distance.
19. The semiconductor integrated circuit according to claim 18 , wherein:
the semiconductor integrated circuit is a rectangle having four sides;
same kind of I/O circuits, which are either the n-pad I/O circuits or the m-pad I/O circuits, are arranged along one pair of sides of two pairs of sides facing each other; and
I/O circuits different in pad number from either the n-pad I/O circuits or the m-pad I/O circuits arranged along the one pair of sides are arranged along one side of another pair of sides.
20. The semiconductor integrated circuit according to claim 18 , wherein:
a plurality of n-pad I/O circuits are arranged side by side along one side of the semiconductor integrated circuit; and
an arrangement pitch of the plurality of n-pad I/O circuits arranged side by side along the one side is set in consideration of an arrangement pitch of a plurality of I/O circuits arranged along one side of another semiconductor integrated circuit.
21. The semiconductor integrated circuit according to claim 18 , wherein:
a plurality of n-pad I/O circuits and a plurality of m-pad I/O circuits are arranged side by side; and
on an entirety of the plurality of n-pad I/O circuits and the plurality of m-pad I/O circuits, a plurality of pads are arranged in a direction toward the internal circuit, a multiplicity of pads arranged in the plurality of n-pad I/O circuits are arranged in zigzag relationship, and a multiplicity of pads arranged in the plurality of m-pad I/O circuits are arranged in zigzag relationship.
22. The semiconductor integrated circuit according to claim 18 , wherein on an entirety of the included n-pad I/O circuits and the m-pad I/O circuits, a total number of pads positioned in a predetermined row and a total number of pads positioned in a row numbered one more than the predetermined row differ from each other.
23. The semiconductor integrated circuit according to claim 18 , wherein the n-pad I/O circuit and the m-pad I/O circuit differ from each other in width in an arrangement direction.
24. The semiconductor integrated circuit according to claim 18 , wherein total gate widths of transistors each having a drain connected directly to a pad are equal to each other between the n-pad I/O circuit and the m-pad I/O circuit.
25. The semiconductor integrated circuit according to claim 18 , wherein gate lengths of transistors that realize a same function are equal to each other between the n-pad I/O circuit and the m-pad I/O circuit.
26. The semiconductor integrated circuit according to claim 18 , wherein gate widths of transistors that realize a same function are equal to each other between the n-pad I/O circuit and the m-pad I/O circuit.
27. The semiconductor integrated circuit according to claim 18 , wherein:
a width of the n-pad circuit in a direction of arrangement of the n-pad I/O circuits is larger than a width of the m-pad circuit in a direction of arrangement of the m-pad I/O circuits; and
a height in the direction toward the internal circuit of the n-pad I/O circuit is less than a height in the direction toward the internal circuit of the m-pad I/O circuit.
28. A multi-chip module, comprising:
a semiconductor chip constituting the semiconductor integrated circuit according to claim 20 ; and
a semiconductor chip constituting another semiconductor integrated circuit,
wherein the plurality of n-pad I/O circuits arranged along the one side of the semiconductor integrated circuit according to claim 23 and a plurality of I/O circuits arranged along one side of the another semiconductor integrated circuit face each other and are connected by a chip-to-chip interconnect.
29. The semiconductor integrated circuit according to claim 24 , wherein in the n-pad I/O circuit and the m-pad I/O circuit:
transistors of a same conductive type each having a drain connected directly to a pad are in multifinger structures; and
gate widths are equal to each other between the multifinger structures.
30. A semiconductor integrated circuit, comprising:
an internal circuit; and
a plurality of input/output (I/O) circuits that are arranged side by side outside the internal circuit, that output a signal of the internal circuit to outside or input a signal of outside to the internal circuit, and on which pads are arrangeable,
the plurality of I/O circuits including at least two kinds of I/O circuit differing in height in a direction toward the internal circuit, the at least two kinds of I/O circuit including:
an n-pad I/O circuit on which the n-pads (n being an integer equal to or larger than one) are arranged in a direction toward the internal circuit, and
an m-pad I/O circuit on which the m-pads (m being an integer larger than n) are arranged in a direction toward the internal circuit,
wherein:
each of the n-pad I/O circuit and the m-pad I/O circuit includes power source wirings extending in a direction of arrangement of the I/O circuits, and at least one of the power source wirings is positioned at a different height from an outer edge between the n-pad I/O circuit and the m-pad I/O circuit; and
a protection circuit for electrostatic discharge protection is arranged between the n-pad I/O circuit and the m-pad I/O circuit arranged side by side adjacent to each other.
31. The semiconductor integrated circuit according to claim 30 , wherein:
the semiconductor integrated circuit is a rectangle having four sides;
same kind of I/O circuits, which are either the n-pad I/O circuits or the m-pad I/O circuits, are arranged along one pair of sides of two pairs of sides facing each other; and
I/O circuits different in pad number from either the n-pad I/O circuits or the m-pad I/O circuits arranged along the one pair of sides are arranged along one side of another pair of sides.
32. The semiconductor integrated circuit according to claim 30 , wherein:
a plurality of n-pad I/O circuits are arranged side by side along one side of the semiconductor integrated circuit; and
an arrangement pitch of the plurality of n-pad I/O circuits arranged side by side along the one side is set in consideration of an arrangement pitch of a plurality of I/O circuits arranged along one side of another semiconductor integrated circuit.
33. The semiconductor integrated circuit according to claim 30 , wherein:
a plurality of n-pad I/O circuits and a plurality of m-pad I/O circuits are arranged side by side; and
on an entirety of the plurality of n-pad I/O circuits and the plurality of m-pad I/O circuits, a plurality of pads are arranged in a direction toward the internal circuit, a multiplicity of pads arranged in the plurality of n-pad I/O circuits are arranged in zigzag relationship, and a multiplicity of pads arranged in the plurality of m-pad I/O circuits are arranged in zigzag relationship.
34. The semiconductor integrated circuit according to claim 30 , wherein on an entirety of the included n-pad I/O circuits and the m-pad I/O circuits, a total number of pads positioned in a predetermined row and a total number of pads positioned in a row numbered one more than the predetermined row differ from each other.
35. The semiconductor integrated circuit according to claim 30 , wherein the n-pad I/O circuit and the m-pad I/O circuit differ from each other in width in an arrangement direction.
36. The semiconductor integrated circuit according to claim 30 , wherein total gate widths of transistors each having a drain connected directly to a pad are equal to each other between the n-pad I/O circuit and the m-pad I/O circuit.
37. The semiconductor integrated circuit according to claim 30 , wherein gate lengths of transistors that realize a same function are equal to each other between the n-pad I/O circuit and the m-pad I/O circuit.
38. The semiconductor integrated circuit according to claim 30 , wherein gate widths of transistors that realize a same function are equal to each other between the n-pad I/O circuit and the m-pad I/O circuit.
39. The semiconductor integrated circuit according to claim 30 , wherein:
a width of the n-pad circuit in a direction of arrangement of the n-pad I/O circuits is larger than a width of the m-pad circuit in a direction of arrangement of the m-pad I/O circuits; and
a height in the direction toward the internal circuit of the n-pad I/O circuit is less than a height in the direction toward the internal circuit of the m-pad I/O circuit.
40. A multi-chip module, comprising:
a semiconductor chip constituting the semiconductor integrated circuit according to claim 32 ; and
a semiconductor chip constituting another semiconductor integrated circuit,
wherein the plurality of n-pad I/O circuits arranged along the one side of the semiconductor integrated circuit according to claim 34 and a plurality of I/O circuits arranged along one side of the another semiconductor integrated circuit face each other and are connected by a chip-to-chip interconnect.
41. The semiconductor integrated circuit according to claim 36 , wherein in the n-pad I/O circuit and the m-pad I/O circuit:
transistors of a same conductive type each having a drain connected directly to a pad are in multifinger structures; and
gate widths are equal to each other between the multifinger structures.
42. A semiconductor integrated circuit, comprising:
an internal circuit; and
a plurality of input/output (I/O) circuits that are arranged side by side outside the internal circuit, that output a signal of the internal circuit to outside or input a signal of outside to the internal circuit, and on which pads are arrangeable,
the plurality of I/O circuits including at least two kinds of I/O circuit differing in height in a direction toward the internal circuit, the at least two kinds of I/O circuit including:
an n-pad I/O circuit on which the n-pads (n being an integer equal to or larger than one) are arranged in a direction toward the internal circuit, and
an m-pad I/O circuit on which the m-pads (m being an integer larger than n) are arranged in a direction toward the internal circuit,
wherein:
total gate widths of transistors each having a drain connected directly to a pad are equal to each other between the n-pad I/O circuit and the m-pad I/O circuit, and
wherein in the n-pad I/O circuit and the m-pad I/O circuit:
transistors of a same conductive type each having a drain connected directly to a pad are in multifinger structures; and
gate widths are equal to each other between the multifinger structures.